Lines Matching full:spill
104 // Integer spill area is handled with "pop".
315 // Determine the sizes of each callee-save spill areas and record which frame
316 // belongs to which callee-save spill areas.
348 // Determine spill area sizes.
392 // Determine starting offsets of spill areas.
518 // For iOS, FP is R7, which has now been stored in spill area 1.
520 // into spill area 1, including the FP in R11. In either case, it
735 // Move SP to start of FP callee save spill area.
857 // since it's available. This is handy for the emergency spill slot, in
1061 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
1063 /// pointer pointing to the d8 spill slot.
1075 // Mark the D-register spill slots as properly aligned. Since MFI computes
1097 // Move the stack pointer to the d8 spill slot, and align it at the same
1134 // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1189 // The last spill instruction inserted should kill the scratch register r4.
1202 assert(MI->mayStore() && "Expecting spill instruction");
1208 assert(MI->mayStore() && "Expecting spill instruction");
1211 assert(MI->mayStore() && "Expecting spill instruction");
1242 // Materialize the address of the d8 spill slot into the scratch register r4.
1325 // The code above does not insert spill code for the aligned DPRCS2 registers.
1428 // In functions that realign the stack, it can be an advantage to spill the
1438 // Naked functions don't spill callee-saved registers.
1455 // We always spill contiguous d-registers starting from d8. Count how many
1469 // Spill the first NumSpills D-registers after realigning the stack.
1480 // This tells PEI to spill the FP as if it is any other callee-save register
1499 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
1500 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
1509 // Spill LR if Thumb1 function uses variable length argument lists.
1513 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know
1515 // enough. If there anything changes it, it'll be a spill, which implies
1524 // See if we can spill vector registers to aligned stack.
1527 // Spill the BasePtr if it's used.
1531 // Don't spill FP if the frame can be eliminated. This is determined
1603 // offset, make sure a register (or a spill slot) is available for the
1609 // that case to want a spill slot (or register) as well. Similarly, if
1627 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1651 // of GPRs, spill one extra callee save GPR so we won't have to pad between
1658 // Don't spill high register if the function is thumb. In the case of
1678 // to materialize a stack offset. If so, either spill one additional
1679 // callee-saved register or reserve a special spill slot to facilitate
1680 // register scavenging. Thumb1 needs a spill slot for stack pointer
1683 // If any non-reserved CS register isn't spilled, just spill one or two
1713 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
