Lines Matching refs:MBB
123 static void emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB,
131 emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
134 emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
138 static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB,
144 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
208 void emitDefCFAOffsets(MachineModuleInfo &MMI, MachineBasicBlock &MBB,
218 BuildMI(MBB, std::next(Info.I), dl,
236 MachineBasicBlock &MBB,
258 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
263 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
272 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
276 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
284 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg)
291 MachineBasicBlock &MBB) const {
292 MachineBasicBlock::iterator MBBI = MBB.begin();
331 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
339 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize),
344 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP);
386 MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push;
422 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize,
453 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
457 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
466 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
474 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
478 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
486 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr),
500 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
526 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush,
534 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
541 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
576 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
600 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
622 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
633 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP);
652 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign,
662 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
664 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign,
666 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
680 BuildMI(MBB, MBBI, dl,
685 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
698 MachineBasicBlock &MBB) const {
718 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
719 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
723 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize);
727 if (MBBI != MBB.begin()) {
730 } while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
748 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
760 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
762 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
769 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
772 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
778 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
791 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize());
799 emitSPUpdate(isARM, MBB, MBBI, dl, TII, ArgRegsSaveSize);
888 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
896 MachineFunction &MF = *MBB.getParent();
925 MBB.addLiveIn(Reg);
940 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
945 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
957 if (MI != MBB.begin())
962 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
969 MachineFunction &MF = *MBB.getParent();
976 if (MBB.end() != MI) {
1002 if (MBB.succ_empty()) {
1025 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
1029 if (DeleteRet && MI != MBB.end()) {
1040 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
1056 if (MI != MBB.end())
1064 static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
1069 MachineFunction &MF = *MBB.getParent();
1071 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1111 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1121 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);
1128 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1143 MBB.addLiveIn(SupReg);
1144 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
1161 MBB.addLiveIn(SupReg);
1162 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
1173 MBB.addLiveIn(SupReg);
1174 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
1182 MBB.addLiveIn(NextReg);
1184 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
1224 static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
1229 MachineFunction &MF = *MBB.getParent();
1231 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1251 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1261 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1277 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1288 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
1296 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1303 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1310 MachineFunction &MF = *MBB.getParent();
1318 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
1320 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
1322 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
1329 emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1334 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1341 MachineFunction &MF = *MBB.getParent();
1349 emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1354 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1356 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1358 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1368 for (auto &MBB : MF) {
1369 for (auto &MI : MBB)
1383 for (auto &MBB : MF) {
1384 for (auto &MI : MBB) {
1731 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1761 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,
1767 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,
1772 MBB.erase(I);
1908 for (MachineBasicBlock *MBB : BeforePrologueRegion) {
1910 MBB->sortUniqueLiveIns();
1913 MBB->ReplaceUsesOfBlockWith(&PrologueMBB, AddedBlocks[0]);
2153 // Organizing MBB lists
