Lines Matching full:gpr
348 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
550 let MIOperandInfo = (ops GPR, i32imm);
561 let MIOperandInfo = (ops GPR, GPR, i32imm);
572 let MIOperandInfo = (ops GPR, i32imm);
816 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
837 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
891 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
908 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
909 // the GPR is purely vestigal at this point.
930 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
955 let MIOperandInfo = (ops GPR, i32imm);
973 let MIOperandInfo = (ops GPR:$base, i32imm);
990 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1000 let MIOperandInfo = (ops GPR);
1010 let MIOperandInfo = (ops GPR:$addr, i32imm);
1018 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
1094 let MIOperandInfo = (ops GPR:$addr, i32imm);
1105 let MIOperandInfo = (ops GPR:$addr, i32imm);
1169 let MIOperandInfo = (ops GPR, i32imm);
1180 let MIOperandInfo = (ops GPR:$base);
1231 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1233 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1244 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1246 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1259 def rsi : AsI1<opcod, (outs GPR:$Rd),
1260 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1262 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1275 def rsr : AsI1<opcod, (outs GPR:$Rd),
1276 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1278 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1304 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1306 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1317 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1331 def rsi : AsI1<opcod, (outs GPR:$Rd),
1332 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1334 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1347 def rsr : AsI1<opcod, (outs GPR:$Rd),
1348 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1350 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1374 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1376 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1379 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1381 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1385 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1386 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1388 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1392 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1393 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1395 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1407 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1409 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1412 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1413 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1415 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1416 GPR:$Rn))]>,
1419 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1420 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1422 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1423 GPR:$Rn))]>,
1436 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1438 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1450 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1452 [(opnode GPR:$Rn, GPR:$Rm)]>,
1468 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1470 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1536 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1538 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1553 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1567 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1569 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1580 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1582 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1595 def rsi : AsI1<opcod, (outs GPR:$Rd),
1596 (ins GPR:$Rn, so_reg_imm:$shift),
1598 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1637 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1639 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1650 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1663 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1665 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1678 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR
1680 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1702 // GPR and a constrained immediate so that we can use this to match
1704 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1706 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1714 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1716 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1732 // GPR and a constrained immediate so that we can use this to match
1764 // GPR and a constrained immediate so that we can use this to match
1767 (ins GPR:$Rt, addrmode_imm12:$addr),
1769 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1777 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1779 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1793 // GPR and a constrained immediate so that we can use this to match
1892 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
2061 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
2063 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
2067 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
2069 [(set GPR:$dst, (load addrmodepc:$addr))]>;
2071 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2073 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
2075 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2077 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
2079 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2081 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
2083 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
2085 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
2088 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2089 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
2091 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2092 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
2095 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
2096 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
2107 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
2123 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
2126 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
2160 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
2161 [(brind GPR:$dst)]>,
2168 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
2204 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2206 [(ARMcall GPR:$func)]>,
2213 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2215 [(ARMcall_pred GPR:$func)]>,
2264 (ins GPR:$target, i32imm:$jt),
2266 [(ARMbrjt GPR:$target, tjumptable:$jt)]>,
2276 (ins GPR:$target, GPR:$idx, i32imm:$jt),
2278 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>,
2297 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2323 (BX GPR:$dst)>, Sched<[WriteBr]>,
2399 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2482 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2494 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2496 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2499 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2501 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2503 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2505 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2509 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2514 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2516 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2518 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2524 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2535 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2547 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2565 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2592 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2604 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2625 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2638 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2657 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2677 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2693 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2713 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2730 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2761 (outs GPR:$Rt)>;
2765 (outs GPR:$Rt)>;
2770 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2772 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2776 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2786 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2787 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2799 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2800 (ins GPR:$Rt, ldst_so_reg:$addr),
2812 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2813 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2830 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2831 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2855 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2857 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2859 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2861 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2863 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2865 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2867 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2869 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2879 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2880 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2882 [(set GPR:$Rn_wb,
2883 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2884 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2885 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2887 [(set GPR:$Rn_wb,
2888 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2889 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2890 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2892 [(set GPR:$Rn_wb,
2893 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2894 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2895 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2897 [(set GPR:$Rn_wb,
2898 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2899 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2900 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2902 [(set GPR:$Rn_wb,
2903 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2908 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2909 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2922 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2923 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2927 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2941 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2942 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2955 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2956 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2974 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2975 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2994 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2995 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3012 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3015 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3016 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
3035 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
3036 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
3054 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
3057 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3058 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
3067 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
3068 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3082 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3084 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3086 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
3098 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3107 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3118 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3127 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3138 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3147 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3158 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3167 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3196 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3199 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3217 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3259 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3261 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3274 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3275 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
3286 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3289 [(set GPR:$Rd, imm0_65535:$imm)]>,
3302 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3305 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3311 (ins GPR:$src, imm0_65535_expr:$imm),
3315 (or (and GPR:$src, 0xffff),
3328 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3329 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3334 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3338 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3339 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3346 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3347 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3349 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3350 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3388 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3389 // (UXTB16r_rot GPR:$Src, 3)>;
3390 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3391 (UXTB16 GPR:$Src, 1)>;
3485 def : ARMPat<(add GPR:$src, mod_imm_neg:$imm),
3486 (SUBri GPR:$src, mod_imm_neg:$imm)>;
3487 def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm),
3488 (SUBSri GPR:$src, mod_imm_neg:$imm)>;
3490 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3491 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3493 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3494 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3500 def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR),
3501 (SBCri GPR:$src, mod_imm_not:$imm)>;
3502 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3503 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
3513 // GPR:$dst = GPR:$a op GPR:$b
3594 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3608 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3710 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3713 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3725 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3728 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3742 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3744 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3753 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3755 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3766 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3768 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3782 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
3784 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3793 def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
3794 (BICri GPR:$src, mod_imm_not:$imm)>;
3873 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR
3875 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3890 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3891 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3895 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3896 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3901 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3902 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3904 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3907 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3908 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3910 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3916 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3917 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3920 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3921 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3925 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3926 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3941 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3942 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3944 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3947 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3948 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3950 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3958 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3960 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3965 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3971 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3972 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3974 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3977 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3978 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3982 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3983 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3987 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3988 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3993 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3995 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3996 (sext_inreg GPR:$Rm, i16)))]>,
3999 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4001 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
4002 (sra GPR:$Rm, (i32 16))))]>,
4005 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4007 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4008 (sext_inreg GPR:$Rm, i16)))]>,
4011 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4013 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
4014 (sra GPR:$Rm, (i32 16))))]>,
4017 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4022 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4032 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4034 [(set GPRnopc:$Rd, (add GPR:$Ra,
4040 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4043 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
4048 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4051 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4056 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4059 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
4064 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4070 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4144 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4148 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4178 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4180 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4183 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4185 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4192 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4194 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4197 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4199 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
4203 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4205 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4209 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4211 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4217 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4218 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4221 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4223 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4227 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4228 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4229 (REVSH GPR:$Rm)>;
4343 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
4344 (CMPri GPR:$src, mod_imm:$imm)>;
4345 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4346 (CMPrr GPR:$src, GPR:$rhs)>;
4347 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4348 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4349 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4350 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4354 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4356 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4370 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4373 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4388 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4391 GPR:$Rn, so_reg_imm:$shift)]>,
4429 def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm),
4430 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4432 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm),
4433 (CMNri GPR:$src, mod_imm_neg:$imm)>;
4448 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4450 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4454 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4455 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4464 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4465 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4467 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4471 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4472 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4474 [(set GPR:$Rd,
4475 (ARMcmov GPR:$false, so_reg_imm:$shift,
4478 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4479 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4481 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4488 : ARMPseudoInst<(outs GPR:$Rd),
4489 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4491 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4497 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4498 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4500 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm,
4507 : ARMPseudoInst<(outs GPR:$Rd),
4508 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4510 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4515 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4516 (ins GPR:$false, mod_imm:$imm, cmovpred:$p),
4518 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm,
4581 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4586 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4588 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4597 (outs GPR:$newdst, GPR:$newsrc),
4598 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops),
4600 [(set GPR:$newdst, GPR:$newsrc,
4601 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>;
4659 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4661 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4662 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4664 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4665 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4667 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4674 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4676 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>;
4677 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4679 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>;
4680 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4682 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>;
4691 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4693 [(set GPR:$Rd, (strex_1 GPR:$Rt,
4695 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4697 [(set GPR:$Rd, (strex_2 GPR:$Rt,
4699 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4701 [(set GPR:$Rd, (strex_4 GPR:$Rt,
4704 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4709 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4711 [(set GPR:$Rd,
4712 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4713 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4715 [(set GPR:$Rd,
4716 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4717 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4719 [(set GPR:$Rd,
4720 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4722 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4735 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4736 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4737 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4738 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4740 def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4741 (STLEXB GPR:$Rt, addr_offset_none:$addr)>;
4742 def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4743 (STLEXH GPR:$Rt, addr_offset_none:$addr)>;
4769 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4770 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4771 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
5026 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5028 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5032 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5070 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5072 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
5076 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5209 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5271 def WIN__DBZCHK : PseudoInst<(outs), (ins GPR:$divisor), NoItinerary,
5272 [(win__dbzchk GPR:$divisor)]>;
5309 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5311 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5318 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5320 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5327 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5329 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5351 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5352 4, IIC_Br, [(brind GPR:$dst)],
5353 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5363 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5364 [(set GPR:$dst, (arm_i32imm:$src))]>,
5367 def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i,
5368 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>,
5376 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5378 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5381 def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5383 [(set GPR:$dst,
5388 def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5390 [(set GPR:$dst,
5395 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5397 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5436 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5437 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5438 (SMULBB GPR:$a, GPR:$b)>;
5440 (SMULBB GPR:$a, GPR:$b)>;
5441 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5442 (sra GPR:$b, (i32 16))),
5443 (SMULBT GPR:$a, GPR:$b)>;
5444 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5445 (SMULBT GPR:$a, GPR:$b)>;
5446 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5447 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5448 (SMULTB GPR:$a, GPR:$b)>;
5449 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5450 (SMULTB GPR:$a, GPR:$b)>;
5452 def : ARMV5MOPat<(add GPR:$acc,
5453 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5454 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5455 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5456 def : ARMV5MOPat<(add GPR:$acc,
5458 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5459 def : ARMV5MOPat<(add GPR:$acc,
5460 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5461 (sra GPR:$b, (i32 16)))),
5462 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5463 def : ARMV5MOPat<(add GPR:$acc,
5464 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5465 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5466 def : ARMV5MOPat<(add GPR:$acc,
5467 (mul (sra GPR:$a, (i32 16)),
5468 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5469 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5470 def : ARMV5MOPat<(add GPR:$acc,
5471 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5472 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5476 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5481 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5482 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5483 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5484 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5485 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5486 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5487 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5490 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5491 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5493 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5494 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5495 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5496 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5509 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5510 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5511 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5512 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5513 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5514 (STRH GPR:$val, addrmode3:$ptr)>;
5515 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5516 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5517 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5518 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5587 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5589 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5591 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5600 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5602 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5604 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5658 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
5661 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
5664 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
5667 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm,
5672 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5674 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
5688 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5691 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5694 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5697 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5701 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5719 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5736 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5739 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5742 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5745 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5754 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
5756 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>;
