Lines Matching defs:Regs
140 DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs);
144 DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs) const;
534 /// Return the first register of class \p RegClass that is not in \p Regs.
566 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs,
568 for (const std::pair<unsigned, bool> &R : Regs)
575 /// Regs as the register operands that would be loaded / stored. It returns
580 DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs) {
581 unsigned NumRegs = Regs.size();
595 if (isThumb1 && isi32Load(Opcode) && ContainsReg(Regs, Base)) {
636 NewBase = Regs[NumRegs-1].first;
641 // The merged instruction does not exist yet but will use several Regs if
644 for (const std::pair<unsigned, bool> &R : Regs)
673 (!isi32Store(Opcode) || !ContainsReg(Regs, Base));
743 assert(!(ContainsReg(Regs, Base)) && "Thumb1 can't LDM ! with Base in Regs");
767 for (const std::pair<unsigned, bool> &R : Regs)
776 DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs) const {
781 assert(Regs.size() == 2);
785 MIB.addReg(Regs[0].first, RegState::Define)
786 .addReg(Regs[1].first, RegState::Define);
788 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second))
789 .addReg(Regs[1].first, getKillRegState(Regs[1].second));
800 SmallVector<std::pair<unsigned, bool>, 8> Regs;
811 Regs.push_back(std::make_pair(Reg, IsKill));
848 Opcode, Pred, PredReg, DL, Regs);
851 Opcode, Pred, PredReg, DL, Regs);
