Lines Matching refs:MBB
42 emitSPUpdate(MachineBasicBlock &MBB,
47 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
53 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
76 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
79 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
83 MBB.erase(I);
87 MachineBasicBlock &MBB) const {
88 MachineBasicBlock::iterator MBBI = MBB.begin();
122 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
127 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
134 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
139 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
173 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
202 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
230 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
241 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
248 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
255 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
267 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
273 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
297 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
324 MachineBasicBlock &MBB) const {
325 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
326 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
343 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
346 if (MBBI != MBB.begin()) {
349 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
368 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
370 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
374 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
378 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
379 &MBB.front() != MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
382 emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
384 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
389 bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
395 bool Thumb1FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
396 if (!needPopSpecialFixUp(*MBB.getParent()))
399 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
417 bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
419 MachineFunction &MF = *MBB.getParent();
433 auto MBBI = MBB.getFirstTerminator();
436 if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)
443 assert(MBB.succ_size() == 1);
444 if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)
456 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET)));
463 MBB.erase(MBBI);
470 UsedRegs.addLiveOuts(&MBB, /*AddPristines*/ true);
481 if (MBBI != MBB.end()) {
483 auto InstUpToMBBI = MBB.end();
528 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
533 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) {
538 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP)));
549 MBB.erase(MIB.getInstr());
551 MBB.erase(MBBI);
552 MBBI = AddDefaultPred(BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET)));
556 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
559 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
561 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
566 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
574 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
584 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
594 MachineFunction &MF = *MBB.getParent();
601 MBB.addLiveIn(Reg);
610 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
617 MachineFunction &MF = *MBB.getParent();
622 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
630 if (MBB.succ_empty()) {
639 if (MI != MBB.end())
641 MI = MBB.erase(MI);
654 MBB.insert(MI, &*MIB);
