Lines Matching refs:Entry
151 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
156 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
161 const ReduceEntry &Entry);
164 const ReduceEntry &Entry, bool LiveCPSR, bool IsSelfLoop);
169 const ReduceEntry &Entry, bool LiveCPSR,
175 const ReduceEntry &Entry, bool LiveCPSR,
298 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
301 if ((is2Addr && Entry.PredCC2 == 0) ||
302 (!is2Addr && Entry.PredCC1 == 0)) {
321 } else if ((is2Addr && Entry.PredCC2 == 2) ||
322 (!is2Addr && Entry.PredCC1 == 2)) {
371 const ReduceEntry &Entry) {
380 unsigned Opc = Entry.NarrowOpc1;
382 uint8_t ImmLimit = Entry.Imm1Limit;
384 switch (Entry.WideOpc) {
390 Opc = Entry.NarrowOpc2;
391 ImmLimit = Entry.Imm2Limit;
453 Opc = Entry.NarrowOpc2; // tPOP_RET
465 (Entry.WideOpc == ARM::t2LDMIA_UPD ||
466 Entry.WideOpc == ARM::t2STMDB_UPD)) {
467 Opc = Entry.NarrowOpc2; // tPOP or tPUSH
470 (Entry.WideOpc != ARM::t2LDMIA_UPD &&
471 Entry.WideOpc != ARM::t2STMIA_UPD)) {
509 if (Entry.WideOpc == ARM::t2STMIA)
545 const ReduceEntry &Entry,
552 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
554 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
589 if (Entry.LowRegs1 && !VerifyLowRegs(MI))
593 return ReduceLoadStore(MBB, MI, Entry);
604 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
609 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
621 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
627 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
633 // are prioritized, but the table assumes a unique entry for each
634 // source insn opcode. So for now, we hack a local entry record to use.
639 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
647 const ReduceEntry &Entry,
653 if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
689 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
691 if (Entry.Imm2Limit) {
693 unsigned Limit = (1 << Entry.Imm2Limit) - 1;
698 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
703 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2);
724 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
729 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
766 const ReduceEntry &Entry,
771 if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
777 if (Entry.Imm1Limit)
778 Limit = (1 << Entry.Imm1Limit) - 1;
789 if (Entry.LowRegs1 && !isARMLowRegister(Reg))
799 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
819 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
824 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
913 const ReduceEntry &Entry
916 if (Entry.Special)
917 return ReduceSpecial(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
920 if (Entry.NarrowOpc2 &&
921 ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
925 if (Entry.NarrowOpc1 &&
926 ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
