Lines Matching full:_dst_
324 : V6_LDInst <(outs RC:$dst, IntRegs:$_dst_),
326 "$src1 = $_dst_">;
390 : V6_STInst <(outs IntRegs:$_dst_),
393 "$src1 = $_dst_">, NewValueRel;
431 : V6_STInst <(outs IntRegs:$_dst_),
434 "$src1 = $_dst_">, NewValueRel {
465 : V6_STInst<(outs IntRegs:$_dst_),
469 "$src2 = $_dst_">, NewValueRel {
528 : V6_STInst <(outs IntRegs:$_dst_),
532 "$src2 = $_dst_">;
569 : V6_STInst <(outs IntRegs:$_dst_),
573 "$src2 = $_dst_"> , NewValueRel {
615 : V6_LDInst <(outs VectorRegs:$dst, IntRegs:$_dst_),
617 "$src1 = $_dst_">, NewValueRel;
648 : V6_STInst <(outs IntRegs:$_dst_),
651 "$src1 = $_dst_">, NewValueRel;
670 : V6_STInst <(outs IntRegs:$_dst_),
673 "$src1 = $_dst_">, NewValueRel;
686 : V6_STInst<(outs IntRegs:$_dst_),
690 "$src2 = $_dst_">, NewValueRel {
718 : V6_STInst <(outs IntRegs:$_dst_),
722 "$src2 = $_dst_">, NewValueRel;
737 : V6_STInst <(outs IntRegs:$_dst_),
741 "$src2 = $_dst_">, NewValueRel {
