Lines Matching refs:Index
330 // Helper function that checks if the value of a vector index is within the
588 k_RegisterIndex, /// A register index in one or more RegKind.
612 unsigned Index; /// Index into the register class
642 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, RegKind RegKind,
647 Op->RegIdx.Index = Index;
660 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc);
662 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
670 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
678 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
686 if (RegIdx.Index % 2 != 0)
689 .getRegister(RegIdx.Index / 2);
697 .getRegister(RegIdx.Index);
705 .getRegister(RegIdx.Index);
713 .getRegister(RegIdx.Index);
721 .getRegister(RegIdx.Index);
731 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
739 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
747 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
755 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
763 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
771 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
779 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
787 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
795 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
803 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
866 if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)
990 if (isGPRAsmReg() && RegIdx.Index == 0)
1104 if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&
1143 return RegIdx.Index;
1159 createNumericReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
1161 DEBUG(dbgs() << "createNumericReg(" << Index << ", ...)\n");
1162 return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser);
1168 createGPRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
1170 return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser);
1176 createFGRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
1178 return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser);
1184 createHWRegsReg(unsigned Index, const MCRegisterInfo *RegInfo,
1186 return CreateReg(Index, RegKind_HWRegs, RegInfo, S, E, Parser);
1192 createFCCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
1194 return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser);
1200 createACCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
1202 return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser);
1208 createMSA128Reg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
1210 return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser);
1216 createMSACtrlReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S,
1218 return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser);
1256 Op->RegIdx.Index = RegNo;
1263 return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
1268 return ((RegIdx.Index >= 2 && RegIdx.Index <= 7)
1269 || RegIdx.Index == 16 || RegIdx.Index == 17);
1274 return (RegIdx.Index == 0 ||
1275 (RegIdx.Index >= 2 && RegIdx.Index <= 7) ||
1276 RegIdx.Index == 17);
1281 return (RegIdx.Index == 0 || (RegIdx.Index >= 2 && RegIdx.Index <= 3) ||
1282 (RegIdx.Index >= 16 && RegIdx.Index <= 20));
1286 return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;
1289 return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31;
1292 return isRegIdx() && RegIdx.Kind & RegKind_CCR && RegIdx.Index <= 31;
1298 return RegIdx.Index == 0;
1299 return RegIdx.Index <= 7;
1302 return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
1305 return isRegIdx() && RegIdx.Kind & RegKind_COP0 && RegIdx.Index <= 31;
1308 return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
1311 return isRegIdx() && RegIdx.Kind & RegKind_COP3 && RegIdx.Index <= 31;
1314 return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;
1317 return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;
1360 OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ">";
1372 OS << "RegPair<" << RegIdx.Index << "," << RegIdx.Index + 1 << ">";
3794 if (IntVal > 31) // Maximum index for fpu register.
4266 int Index = matchCPURegisterName(Identifier);
4267 if (Index != -1) {
4269 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
4273 Index = matchHWRegsRegisterName(Identifier);
4274 if (Index != -1) {
4276 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
4280 Index = matchFPURegisterName(Identifier);
4281 if (Index != -1) {
4283 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
4287 Index = matchFCCRegisterName(Identifier);
4288 if (Index != -1) {
4290 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
4294 Index = matchACRegisterName(Identifier);
4295 if (Index != -1) {
4297 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
4301 Index = matchMSA128RegisterName(Identifier);
4302 if (Index != -1) {
4304 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
4308 Index = matchMSA128CtrlRegisterName(Identifier);
4309 if (Index != -1) {
4311 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
