Lines Matching full:spill
272 // spill + reload via ldc1
277 // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
281 // allocation so for now we use a spill/reload sequence for all
299 // We re-use the same spill slot each time so that the stack frame doesn't
333 // spill + reload via ldc1
338 // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
342 // allocation so for now we use a spill/reload sequence for all
362 // We re-use the same spill slot each time so that the stack frame doesn't
484 // Insert instructions that spill eh data registers.
588 // Fetch and spill EPC
599 // Fetch and Spill Status
784 // It's killed at the spill, unless the register is RA and return address
812 // Insert the spill to the stack frame.
828 // Make sure the second register scavenger spill slot can be accessed with one
858 // Create spill
862 // Create spill slots for Coprocessor 0 registers if function is an ISR.
867 // Add an emergency spill slot if a pseudo was expanded.
869 // The spill slot should be half the size of the accumulator. If target is
