Lines Matching defs:SrcReg
81 unsigned DestReg, unsigned SrcReg,
87 if (Mips::GPR32RegClass.contains(SrcReg)) {
92 } else if (Mips::CCRRegClass.contains(SrcReg))
94 else if (Mips::FGR32RegClass.contains(SrcReg))
96 else if (Mips::HI32RegClass.contains(SrcReg)) {
98 SrcReg = 0;
99 } else if (Mips::LO32RegClass.contains(SrcReg)) {
101 SrcReg = 0;
102 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
104 else if (Mips::LO32DSPRegClass.contains(SrcReg))
106 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
111 else if (Mips::MSACtrlRegClass.contains(SrcReg))
114 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
136 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
138 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
140 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
143 if (Mips::GPR64RegClass.contains(SrcReg))
145 else if (Mips::HI64RegClass.contains(SrcReg))
146 Opc = Mips::MFHI64, SrcReg = 0;
147 else if (Mips::LO64RegClass.contains(SrcReg))
148 Opc = Mips::MFLO64, SrcReg = 0;
149 else if (Mips::FGR64RegClass.contains(SrcReg))
152 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
161 if (Mips::MSA128BRegClass.contains(SrcReg))
172 if (SrcReg)
173 MIB.addReg(SrcReg, getKillRegState(KillSrc));
181 unsigned SrcReg, bool isKill, int FI,
230 SrcReg = Mips::K0;
233 SrcReg = Mips::K0_64;
236 SrcReg = Mips::K0;
239 SrcReg = Mips::K0_64;
244 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
568 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
582 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
590 unsigned SrcReg = I->getOperand(1).getReg();
596 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
620 .addReg(SrcReg);
