Lines Matching refs:PVT
8359 MVT PVT = getPointerTy(MF->getDataLayout());
8360 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8403 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8404 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8405 const int64_t BPOffset = 4 * PVT.getStoreSize();
8408 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8497 MVT PVT = getPointerTy(MF->getDataLayout());
8498 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8502 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8505 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8506 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8508 (PVT == MVT::i64)
8517 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8518 const int64_t SPOffset = 2 * PVT.getStoreSize();
8519 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8520 const int64_t BPOffset = 4 * PVT.getStoreSize();
8527 if (PVT == MVT::i64) {
8539 if (PVT == MVT::i64) {
8551 if (PVT == MVT::i64) {
8563 if (PVT == MVT::i64) {
8575 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8586 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8587 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));