Lines Matching refs:Static
45 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
48 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
51 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
945 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
1103 static bool isFloatingPointZero(SDValue Op) {
1117 static bool isConstantOrUndef(int Op, int Val) {
1239 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1349 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1638 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1648 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1704 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1955 static bool GetLabelAccessInfo(const TargetMachine &TM,
1985 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
2004 static void setUsesTOCBasePtr(MachineFunction &MF) {
2009 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2013 static SDValue getTOCEntry(SelectionDAG &DAG, SDLoc dl, bool Is64Bit,
2578 static const MCPhysReg ArgRegs[] = {
2605 static const MCPhysReg ArgRegs[] = {
2629 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2634 static const MCPhysReg QFPR[] = {
2640 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2656 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2702 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2757 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2946 static const MCPhysReg GPArgRegs[] = {
2952 static const MCPhysReg FPArgRegs[] = {
3062 static const MCPhysReg GPR[] = {
3066 static const MCPhysReg VR[] = {
3070 static const MCPhysReg VSRH[] = {
3483 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3487 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3491 static const MCPhysReg VR[] = {
3826 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3882 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3908 static void
3928 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3970 static void
4022 static SDValue
4034 static void
4059 static
4088 static bool isFunctionGlobalAddress(SDValue Callee) {
4100 static
4131 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4155 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4303 static
4786 static const MCPhysReg GPR[] = {
4790 static const MCPhysReg VR[] = {
4794 static const MCPhysReg VSRH[] = {
5489 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5493 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5497 static const MCPhysReg VR[] = {
6732 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6736 static const MVT VTys[] = { // canonical VT to use for each size.
6758 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6768 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6778 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6788 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
7006 static const signed char SplatCsts[] = {
7023 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7034 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7045 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7057 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7090 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
7356 static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
8091 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
9142 static std::string getRecipOp(const char *Base, EVT VT) {
9223 static void getBaseWithConstantOffset(SDValue Loc, SDValue &Base,
9235 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
9275 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
9380 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
11549 static const MCPhysReg ScratchRegs[] = {
