Lines Matching refs:SystemZ
1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
34 if (SystemZ::GRH32BitRegClass.contains(Reg))
36 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
44 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
63 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
64 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
96 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
133 DestReg, SrcReg, SystemZ::LR, 32,
177 Opcode = SystemZ::RISBHH;
179 Opcode = SystemZ::RISBHL;
181 Opcode = SystemZ::RISBLH;
227 if (MI->getOpcode() != SystemZ::MVC ||
281 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
380 "SystemZ branch conditions have one component!");
385 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
393 BuildMI(&MBB, DL, get(SystemZ::BRC))
399 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
453 if (RLL && RLL->getOpcode() == SystemZ::LGFR) {
457 if (!RLL || !isShift(RLL, SystemZ::RLL, 31))
461 if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC))
465 if (!IPM || IPM->getOpcode() != SystemZ::IPM)
474 if (MI->modifiesRegister(SystemZ::CC, TRI))
503 case SystemZ::LR: return SystemZ::LOCR;
504 case SystemZ::LGR: return SystemZ::LOCGR;
544 .addReg(SystemZ::CC, RegState::Implicit);
556 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
557 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
558 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
559 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
560 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
564 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
565 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc);
571 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
572 Opcode = SystemZ::LGR;
573 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
574 Opcode = SystemZ::LER;
575 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
576 Opcode = SystemZ::LDR;
577 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
578 Opcode = SystemZ::LXR;
579 else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
580 Opcode = SystemZ::VLR32;
581 else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
582 Opcode = SystemZ::VLR64;
583 else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
584 Opcode = SystemZ::VLR;
644 case SystemZ::NILMux: return LogicOp(32, 0, 16);
645 case SystemZ::NIHMux: return LogicOp(32, 16, 16);
646 case SystemZ::NILL64: return LogicOp(64, 0, 16);
647 case SystemZ::NILH64: return LogicOp(64, 16, 16);
648 case SystemZ::NIHL64: return LogicOp(64, 32, 16);
649 case SystemZ::NIHH64: return LogicOp(64, 48, 16);
650 case SystemZ::NIFMux: return LogicOp(32, 0, 32);
651 case SystemZ::NILF64: return LogicOp(64, 0, 32);
652 case SystemZ::NIHF64: return LogicOp(64, 32, 32);
697 if (Opcode == SystemZ::AHIMux &&
700 MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
701 MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
702 MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
703 MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
705 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
733 NewOpcode = SystemZ::RISBG;
736 NewOpcode = SystemZ::RISBGN;
738 NewOpcode = SystemZ::RISBMux;
763 if ((Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
768 get(SystemZ::AGSI))
785 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) &&
789 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
797 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
798 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
799 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
803 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
814 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
843 get(SystemZ::MVC))
854 get(SystemZ::MVC))
867 int MemOpcode = SystemZ::getMemOpcode(Opcode);
899 case SystemZ::L128:
900 splitMove(MI, SystemZ::LG);
903 case SystemZ::ST128:
904 splitMove(MI, SystemZ::STG);
907 case SystemZ::LX:
908 splitMove(MI, SystemZ::LD);
911 case SystemZ::STX:
912 splitMove(MI, SystemZ::STD);
915 case SystemZ::LBMux:
916 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
919 case SystemZ::LHMux:
920 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
923 case SystemZ::LLCRMux:
924 expandZExtPseudo(MI, SystemZ::LLCR, 8);
927 case SystemZ::LLHRMux:
928 expandZExtPseudo(MI, SystemZ::LLHR, 16);
931 case SystemZ::LLCMux:
932 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
935 case SystemZ::LLHMux:
936 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
939 case SystemZ::LMux:
940 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
943 case SystemZ::STCMux:
944 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
947 case SystemZ::STHMux:
948 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
951 case SystemZ::STMux:
952 expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
955 case SystemZ::LHIMux:
956 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
959 case SystemZ::IIFMux:
960 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
963 case SystemZ::IILMux:
964 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
967 case SystemZ::IIHMux:
968 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
971 case SystemZ::NIFMux:
972 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
975 case SystemZ::NILMux:
976 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
979 case SystemZ::NIHMux:
980 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
983 case SystemZ::OIFMux:
984 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
987 case SystemZ::OILMux:
988 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
991 case SystemZ::OIHMux:
992 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
995 case SystemZ::XIFMux:
996 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
999 case SystemZ::TMLMux:
1000 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1003 case SystemZ::TMHMux:
1004 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1007 case SystemZ::AHIMux:
1008 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1011 case SystemZ::AHIMuxK:
1012 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1015 case SystemZ::AFIMux:
1016 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1019 case SystemZ::CFIMux:
1020 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1023 case SystemZ::CLFIMux:
1024 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1027 case SystemZ::CMux:
1028 expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1031 case SystemZ::CLMux:
1032 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1035 case SystemZ::RISBMux: {
1039 MI->setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1041 MI->setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1047 case SystemZ::ADJDYNALLOC:
1068 case SystemZ::BR:
1069 case SystemZ::J:
1070 case SystemZ::JG:
1071 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
1072 SystemZ::CCMASK_ANY, &MI->getOperand(0));
1074 case SystemZ::BRC:
1075 case SystemZ::BRCL:
1080 case SystemZ::BRCT:
1081 return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
1082 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
1084 case SystemZ::BRCTG:
1085 return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
1086 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
1088 case SystemZ::CIJ:
1089 case SystemZ::CRJ:
1090 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
1093 case SystemZ::CLIJ:
1094 case SystemZ::CLRJ:
1095 return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
1098 case SystemZ::CGIJ:
1099 case SystemZ::CGRJ:
1100 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
1103 case SystemZ::CLGIJ:
1104 case SystemZ::CLGRJ:
1105 return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
1116 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1117 LoadOpcode = SystemZ::L;
1118 StoreOpcode = SystemZ::ST;
1119 } else if (RC == &SystemZ::GRH32BitRegClass) {
1120 LoadOpcode = SystemZ::LFH;
1121 StoreOpcode = SystemZ::STFH;
1122 } else if (RC == &SystemZ::GRX32BitRegClass) {
1123 LoadOpcode = SystemZ::LMux;
1124 StoreOpcode = SystemZ::STMux;
1125 } else if (RC == &SystemZ::GR64BitRegClass ||
1126 RC == &SystemZ::ADDR64BitRegClass) {
1127 LoadOpcode = SystemZ::LG;
1128 StoreOpcode = SystemZ::STG;
1129 } else if (RC == &SystemZ::GR128BitRegClass ||
1130 RC == &SystemZ::ADDR128BitRegClass) {
1131 LoadOpcode = SystemZ::L128;
1132 StoreOpcode = SystemZ::ST128;
1133 } else if (RC == &SystemZ::FP32BitRegClass) {
1134 LoadOpcode = SystemZ::LE;
1135 StoreOpcode = SystemZ::STE;
1136 } else if (RC == &SystemZ::FP64BitRegClass) {
1137 LoadOpcode = SystemZ::LD;
1138 StoreOpcode = SystemZ::STD;
1139 } else if (RC == &SystemZ::FP128BitRegClass) {
1140 LoadOpcode = SystemZ::LX;
1141 StoreOpcode = SystemZ::STX;
1142 } else if (RC == &SystemZ::VR32BitRegClass) {
1143 LoadOpcode = SystemZ::VL32;
1144 StoreOpcode = SystemZ::VST32;
1145 } else if (RC == &SystemZ::VR64BitRegClass) {
1146 LoadOpcode = SystemZ::VL64;
1147 StoreOpcode = SystemZ::VST64;
1148 } else if (RC == &SystemZ::VF128BitRegClass ||
1149 RC == &SystemZ::VR128BitRegClass) {
1150 LoadOpcode = SystemZ::VL;
1151 StoreOpcode = SystemZ::VST;
1162 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1172 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1185 case SystemZ::L: return SystemZ::LT;
1186 case SystemZ::LY: return SystemZ::LT;
1187 case SystemZ::LG: return SystemZ::LTG;
1188 case SystemZ::LGF: return SystemZ::LTGF;
1189 case SystemZ::LR: return SystemZ::LTR;
1190 case SystemZ::LGFR: return SystemZ::LTGFR;
1191 case SystemZ::LGR: return SystemZ::LTGR;
1192 case SystemZ::LER: return SystemZ::LTEBR;
1193 case SystemZ::LDR: return SystemZ::LTDBR;
1194 case SystemZ::LXR: return SystemZ::LTXBR;
1195 case SystemZ::LCDFR: return SystemZ::LCDBR;
1196 case SystemZ::LPDFR: return SystemZ::LPDBR;
1197 case SystemZ::LNDFR: return SystemZ::LNDBR;
1198 case SystemZ::LCDFR_32: return SystemZ::LCEBR;
1199 case SystemZ::LPDFR_32: return SystemZ::LPEBR;
1200 case SystemZ::LNDFR_32: return SystemZ::LNEBR;
1205 case SystemZ::RISBGN: return SystemZ::RISBG;
1256 case SystemZ::CR:
1257 return SystemZ::CRJ;
1258 case SystemZ::CGR:
1259 return SystemZ::CGRJ;
1260 case SystemZ::CHI:
1261 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
1262 case SystemZ::CGHI:
1263 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
1264 case SystemZ::CLR:
1265 return SystemZ::CLRJ;
1266 case SystemZ::CLGR:
1267 return SystemZ::CLGRJ;
1268 case SystemZ::CLFI:
1269 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLIJ : 0;
1270 case SystemZ::CLGFI:
1271 return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLGIJ : 0;
1283 Opcode = SystemZ::LGHI;
1284 else if (SystemZ::isImmLL(Value))
1285 Opcode = SystemZ::LLILL;
1286 else if (SystemZ::isImmLH(Value)) {
1287 Opcode = SystemZ::LLILH;
1291 Opcode = SystemZ::LGFI;
