Lines Matching refs:IndexReg
266 unsigned BaseReg, IndexReg, TmpReg, Scale;
276 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
281 unsigned getIndexReg() { return IndexReg; }
384 // If we already have a BaseReg, then assume this is the IndexReg with
389 assert (!IndexReg && "BaseReg/IndexReg already set!");
390 IndexReg = TmpReg;
421 // If we already have a BaseReg, then assume this is the IndexReg with
426 assert (!IndexReg && "BaseReg/IndexReg already set!");
427 IndexReg = TmpReg;
463 assert (!IndexReg && "IndexReg already set!");
465 IndexReg = Reg;
513 assert (!IndexReg && "IndexReg already set!");
514 IndexReg = TmpReg;
600 // If we already have a BaseReg, then assume this is the IndexReg with
605 assert (!IndexReg && "BaseReg/IndexReg already set!");
606 IndexReg = TmpReg;
714 unsigned IndexReg, unsigned Scale, SMLoc Start,
833 static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg,
837 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
838 if (BaseReg != 0 && IndexReg != 0) {
840 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
841 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
842 IndexReg != X86::RIZ) {
847 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
848 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
849 IndexReg != X86::EIZ){
854 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
855 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
860 IndexReg != X86::SI && IndexReg != X86::DI) ||
862 IndexReg != X86::BX && IndexReg != X86::BP)) {
1016 /*BaseReg=*/basereg, /*IndexReg=*/0, /*Scale=*/1,
1025 /*BaseReg=*/basereg, /*IndexReg=*/0, /*Scale=*/1,
1068 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1107 IndexReg, Scale, Start, End, Size, Identifier,
1121 // bracketed expression (i.e., ImmDisp [ BaseReg + Scale*IndexReg + Disp])
1302 // Parse [ Symbol + ImmDisp ] and [ BaseReg + Scale*IndexReg + ImmDisp ]. We
1341 int IndexReg = SM.getIndexReg();
1345 if (!BaseReg && !IndexReg) {
1352 if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {
1357 IndexReg, Scale, Start, End, Size);
1361 return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1439 /*BaseReg=*/0, /*IndexReg=*/0, /*Scale=*/1,
1461 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0,/*IndexReg=*/0,
1510 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1530 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0, /*IndexReg=*/0,
1559 /*BaseReg=*/1, /*IndexReg=*/0, /*Scale=*/1,
1748 // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1894 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
1955 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
1981 if (ParseRegister(IndexReg, L, L)) return nullptr;
2050 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
2056 if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {
2061 if (SegReg || BaseReg || IndexReg)
2063 IndexReg, Scale, MemStart, MemEnd);
2256 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2268 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
