Lines Matching defs:Opcode
350 // Get opcode and regclass of the output for the given load instruction.
441 // Get opcode and regclass of the output for the given store instruction.
567 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
693 unsigned Opcode = Instruction::UserOp1;
700 Opcode = I->getOpcode();
704 Opcode = C->getOpcode();
714 switch (Opcode) {
853 unsigned Opcode = Instruction::UserOp1;
880 Opcode = I->getOpcode();
884 Opcode = C->getOpcode();
888 switch (Opcode) {
1177 /// opcode that works for the compare (e.g. CMP32ri) otherwise return 0.
1619 unsigned OpDivRem; // The specific DIV/IDIV opcode to use.
1620 unsigned OpSignExtend; // Opcode for sign-extending lowreg into
1622 unsigned OpCopy; // Opcode for copying dividend into lowreg, or
1675 default: llvm_unreachable("Unexpected div/rem opcode");
2113 unsigned Opcode;
2117 Opcode = X86::VCVTSI2SDrr;
2121 Opcode = X86::VCVTSI2SSrr;
2130 fastEmitInst_rr(Opcode, RC, ImplicitDefReg, true, OpReg, false);
3362 // Get opcode and regclass of the output for the given load instruction.
3520 // Get opcode and regclass for the given zero.
