Lines Matching refs:IndexReg
252 /// IndexReg field of the addressing mode will be updated to match in this case.
257 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg,
596 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
615 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
677 if (AM.IndexReg == 0) {
679 AM.IndexReg = getRegForValue(V);
680 return AM.IndexReg != 0;
764 unsigned IndexReg = AM.IndexReg;
796 if (IndexReg == 0 &&
801 IndexReg = getRegForGEPIndex(Op).first;
802 if (IndexReg == 0)
815 AM.IndexReg = IndexReg;
919 (AM.Base.Reg != 0 || AM.IndexReg != 0))
939 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
956 if (AM.IndexReg == 0) {
958 AM.IndexReg = getRegForValue(V);
959 return AM.IndexReg != 0;
3447 AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == nullptr)
3587 if (!MO.isReg() || MO.isDef() || MO.getReg() != AM.IndexReg)
3590 unsigned IndexReg = constrainOperandRegClass(Result->getDesc(),
3592 if (IndexReg == MO.getReg())
3594 MO.setReg(IndexReg);
