Lines Matching defs:Opcode
2314 X86ISD::NodeType opcode = X86ISD::RET_FLAG;
2316 opcode = X86ISD::IRET;
2317 return DAG.getNode(opcode, dl, MVT::Other, RetOps);
3634 unsigned Opcode = Def->getOpcode();
3635 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3636 Opcode == X86::LEA64_32r) &&
3896 static bool isTargetShuffle(unsigned Opcode) {
3897 switch(Opcode) {
4735 /// Calculates the shuffle mask corresponding to the target-specific opcode.
5031 unsigned Opcode = V.getOpcode();
5047 if (isTargetShuffle(Opcode)) {
5067 if (Opcode == ISD::BITCAST) {
5869 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5871 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5872 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5878 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5888 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5908 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6060 unsigned Opcode = Op.getOpcode();
6061 if (Opcode == ISD::UNDEF) {
6066 // Early exit if we found an unexpected opcode.
6067 if (Opcode != ExpectedOpcode)
6917 // The UNDEF opcode check really should be dead code here, but not quite
7452 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7467 V = DAG.getNode(OpCode, DL, ShiftVT, V,
11872 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11898 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
13473 "Wrong opcode for lowering FABS or FNEG.");
13811 unsigned Opcode = 0;
13862 Opcode = X86ISD::INC;
13869 Opcode = X86ISD::DEC;
13876 Opcode = X86ISD::ADD;
13922 case ISD::SUB: Opcode = X86ISD::SUB; break;
13923 case ISD::XOR: Opcode = X86ISD::XOR; break;
13924 case ISD::AND: Opcode = X86ISD::AND; break;
13931 Opcode = X86ISD::OR;
13958 // Use a target machine opcode to prevent further DAGCombine
13980 if (Opcode == 0)
13988 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14770 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
16060 // Change opcode to non-immediate version
16328 // - RM Opcode is specified and
16842 unsigned Opcode;
16847 Opcode = X86ISD::PCMPISTRI;
16851 Opcode = X86ISD::PCMPESTRI;
16855 Opcode = X86ISD::PCMPISTRI;
16859 Opcode = X86ISD::PCMPESTRI;
16863 Opcode = X86ISD::PCMPISTRI;
16867 Opcode = X86ISD::PCMPESTRI;
16871 Opcode = X86ISD::PCMPISTRI;
16875 Opcode = X86ISD::PCMPESTRI;
16879 Opcode = X86ISD::PCMPISTRI;
16883 Opcode = X86ISD::PCMPESTRI;
16889 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16898 unsigned Opcode;
16900 Opcode = X86ISD::PCMPISTRI;
16902 Opcode = X86ISD::PCMPESTRI;
16906 return DAG.getNode(Opcode, dl, VTs, NewOps);
17083 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17087 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17104 if (Opcode == X86ISD::RDTSCP_DAG) {
17258 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17264 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17543 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17544 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17552 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17554 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17566 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17569 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17580 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17583 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17649 // This is storing the opcode for MOV32ri.
17650 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17663 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
18215 unsigned Opcode =
18219 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18222 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18259 // Return true if the required (according to Opcode) shift-imm form is natively
18262 unsigned Opcode) {
18275 return (Opcode == ISD::SRA) ? AShift : LShift;
18282 unsigned Opcode) {
18283 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18286 // Return true if the required (according to Opcode) variable-shift form is
18289 unsigned Opcode) {
18303 return (Opcode == ISD::SRA) ? AShift : LShift;
18412 llvm_unreachable("Unknown shift opcode.");
19536 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19541 return DAG.getNode(OpCode, DL, VT, V,
20336 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
20338 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
20408 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
20409 switch ((X86ISD::NodeType)Opcode) {
20916 default: llvm_unreachable("illegal opcode!");
20953 default: llvm_unreachable("illegal opcode!");
21374 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
21416 // true/false values to select between, and a branch opcode to use.
22376 // Get the X86 opcode to use.
22379 default: llvm_unreachable("illegal opcode!");
23557 unsigned Opcode = BC0.getOpcode();
23562 TLI.isOperationLegal(Opcode, VT)) {
23564 switch (Opcode) {
23983 unsigned Opcode = 0;
23999 Opcode = X86ISD::FMIN;
24007 Opcode = X86ISD::FMIN;
24016 Opcode = X86ISD::FMIN;
24025 Opcode = X86ISD::FMAX;
24037 Opcode = X86ISD::FMAX;
24046 Opcode = X86ISD::FMAX;
24064 Opcode = X86ISD::FMIN;
24071 Opcode = X86ISD::FMIN;
24080 Opcode = X86ISD::FMIN;
24087 Opcode = X86ISD::FMAX;
24099 Opcode = X86ISD::FMAX;
24108 Opcode = X86ISD::FMAX;
24113 if (Opcode)
24114 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
25119 unsigned opcode;
25123 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
25310 unsigned Opcode = N->getOpcode();
25311 switch (Opcode) {
25325 llvm_unreachable("Unexpected opcode");
26798 default: llvm_unreachable("unknown opcode");
27137 unsigned Opcode;
27139 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
27141 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
27143 return DAG.getNode(Opcode, dl, VT, A, B, C);
