Lines Matching refs:Index
1020 // the index is constant. For now custom expand to deal with that.
2792 // If the function takes variable number of arguments, make a frame index for
3339 // Create frame index.
4191 unsigned Index) const {
4195 return (Index == 0 || Index == ResVT.getVectorNumElements());
4246 // The index should be aligned on a vecWidth-bit boundary.
4247 uint64_t Index =
4252 bool Result = (Index * ElSize) % vecWidth == 0;
4264 // The index should be aligned on a vecWidth-bit boundary.
4265 uint64_t Index =
4270 bool Result = (Index * ElSize) % vecWidth == 0;
4296 uint64_t Index =
4303 return Index / NumElemsPerChunk;
4311 uint64_t Index =
4318 return Index / NumElemsPerChunk;
4322 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4328 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4334 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4340 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4451 // This is the index of the first element of the vectorWidth-bit chunk
4467 /// instructions or a simple subregister reference. Idx is an index in the
4500 // This is the index of the first element of the vectorWidth-bit chunk
4511 /// simple superregister reference. Idx is an index in the 128 bits
4518 // For insertion into the zero index (low half) of a 256-bit vector, it is
4591 "Unexpected index value in INSERT_SUBVECTOR");
4598 // to v16i1, index 2)
4870 // Mask only contains negative index if an element is zero.
5024 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5035 int Elt = SV->getMaskElt(Index);
5056 int Elt = ShuffleMask[Index];
5077 return (Index == 0) ? V.getOperand(0)
5081 return V.getOperand(Index);
5201 // zeroable or extract_vector_elt with constant index.
5237 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5656 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5657 /// underlying vector and index.
5660 /// index.
5675 // In this case the vector is the extract_subvector expression and the index
5724 // Quit if non-constant index.
5901 // Update the expected vector extract index.
6910 // If this is an index into a build_vector node (which has the same number
7313 // Get the mod-Size index and lane correct it.
7339 // Compute which of the two target values this index should be assigned
7526 // The extracted elements must start at a valid index and all mask
7626 /// begin and can start from an offseted element index in the input; to
7645 // Check that an index is in same lane as the base offset.
8251 // Determine element insertion src/dst indices. The src index is from the
8625 // Compute the index adjacent to V2Index and in the same half by toggling
8969 // Compute the index of dword with only one word among the three inputs in
9017 // Determine whether the free index is in the flipped dword or the
9018 // unflipped dword based on where the pinned index is. We use this bit
9115 // a dword. We find the adjacent index by toggling the low bit.
9217 // the inputs, place the other input in it. We use (Index XOR 1) to
9218 // compute an adjacent index.
11521 // the case of a store, it's not worth it if the index is a constant 0,
11538 // ExtractPS/pextrq works with constant index.
11559 // variable index can't be handled in mask registers,
11704 // Non constant index. Extend source and destination,
11796 // zero here. The DAG Combiner may combine an extract_elt index into
11824 // PINSR* works with constant index.
12389 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13687 // Quit if without a constant index.
16951 SDValue Index, SDValue ScaleOp, SDValue Chain,
16957 Index.getSimpleValueType().getVectorNumElements());
16977 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16985 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16992 Index.getSimpleValueType().getVectorNumElements());
17008 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17014 SDValue Mask, SDValue Base, SDValue Index,
17022 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17030 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17044 // The ECX register is used to select the index of the performance counter
17151 // Cast the operand to an alloca, and remember the frame index.
17233 //gather(v1, mask, index, base, scale);
17237 SDValue Index = Op.getOperand(4);
17240 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17244 //scatter(base, mask, index, v1, scale);
17248 SDValue Index = Op.getOperand(4);
17251 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17261 SDValue Index = Op.getOperand(3);
17264 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
18508 "Unexpected shuffle index found!");
19281 DAG.getRegister(0, MVT::i32), // Index
19469 // index into a in-register pre-computed pop count table. We then split up the
19473 // to index the in-register table. Next, both are added and the result is a
19503 // The input vector is used as the shuffle mask that index elements into the
19814 SDValue Index = N->getIndex();
19819 MVT IndexVT = Index.getSimpleValueType();
19833 // Expand the index.
19835 Index = ExtendToType(Index, NewIndexVT, DAG);
19848 !Index.getSimpleValueType().is512BitVector()) {
19849 // AVX512F supports only 512-bit vectors. Or data or index should
19850 // be 512 bit wide. If now the both index and data are 256-bit, but
19851 // the vector contains 8 elements, we just sign-extend the index
19853 // Just extend index
19854 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19858 // Index
19860 // Use original index here, do not modify the index twice
19861 Index = ExtendToType(N->getIndex(), NewIndexVT, DAG);
19863 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19883 SDValue Ops[] = {Chain, Src, Mask, BasePtr, Index};
19954 SDValue Index = N->getIndex();
19957 MVT IndexVT = Index.getSimpleValueType();
19964 !Index.getSimpleValueType().is512BitVector()) {
19965 // AVX512F supports only 512-bit vectors. Or data or index should
19966 // be 512 bit wide. If now the both index and data are 256-bit, but
19967 // the vector contains 8 elements, we just sign-extend the index
19969 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19971 N->getOperand(3), Index };
19978 // Index
19980 Index = ExtendToType(Index, NewIndexVT, DAG);
19982 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19996 SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index };
21028 MachineOperand &Index = MI->getOperand(3);
21133 .addOperand(Index)
21158 .addOperand(Index)
21185 .addOperand(Index)
21205 .addOperand(Index)
21241 .addOperand(Index)
21712 .addReg(/*Index=*/0)
21720 .addReg(/*Index=*/0)
22766 int Index = Mask[0];
22767 assert((Index >= 0 || Index == SM_SentinelUndef ||
22768 Index == SM_SentinelZero) &&
22769 "Invalid shuffle index found!");
22773 // If the only shuffle index is equal to SM_SentinelZero then propagate
22776 if (Index == SM_SentinelZero)
23763 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
26501 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
26502 if (!(LIdx == Index && RIdx == Index + 1) &&
26503 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
26892 // BT ignores high bits in the bit index operand.
