Lines Matching refs:SETCC
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
421 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
422 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
423 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
424 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
425 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
426 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
427 setOperationAction(ISD::SETCC , MVT::f128 , Custom);
433 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
736 setOperationAction(ISD::SETCC, VT, Expand);
851 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
852 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
853 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
854 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
1127 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1128 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1129 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1130 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1335 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1474 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1475 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1627 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1628 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1706 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1707 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1822 setTargetDAGCombine(ISD::SETCC);
13752 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13814 // Truncate operations may prevent the merge of the SETCC instruction
13848 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13854 UI->getOpcode() != ISD::SETCC &&
13960 // from the setcc node.
14190 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14214 default: llvm_unreachable("Unexpected SETCC condition");
14247 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14287 default: llvm_unreachable("Unexpected SETCC condition");
14333 default: llvm_unreachable("Unexpected SETCC condition");
14438 // legalizer firstly checks if the first operand in input to the setcc has
14473 // In AVX-512 architecture setcc returns mask with i1 elements,
14481 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14490 default: llvm_unreachable("Unexpected SETCC condition");
14519 default: llvm_unreachable("Unexpected SETCC condition");
14690 && "SetCC type must be 8-bit or 1-bit integer");
14715 // If the input is a setcc, then reuse the input setcc or use a new one with
14717 if (Op0.getOpcode() == X86ISD::SETCC) {
14724 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14728 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14729 return SetCC;
14746 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14749 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14750 return SetCC;
14766 return DAG.getNode(X86ISD::SETCC, DL, Op.getValueType(),
14818 if (Cond.getOpcode() == ISD::SETCC &&
14908 if (Cond.getOpcode() == ISD::SETCC) {
14918 if (Cond.getOpcode() == X86ISD::SETCC &&
14970 // setting operand in place of the X86ISD::SETCC.
14972 if (CondOpcode == X86ISD::SETCC ||
15433 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15439 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15441 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15445 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15446 // 1 and that the SETCC node has a single use.
15451 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15465 if (Cond.getOpcode() == ISD::SETCC) {
15466 // Check for setcc([su]{add,sub,mul}o == 0).
15500 // setting operand in place of the X86ISD::SETCC.
15502 if (CondOpcode == X86ISD::SETCC ||
15628 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15637 } else if (Cond.getOpcode() == ISD::SETCC &&
15668 } else if (Cond.getOpcode() == ISD::SETCC &&
16672 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16674 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16690 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16692 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16758 // or testp pattern and a setcc for the result.
16818 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16819 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16828 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16829 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16890 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16893 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17283 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17286 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17302 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17305 Results.push_back(SetCC);
19053 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
19054 // looks for this combo and may remove the "setcc" instruction if the "setcc"
19108 SDValue SetCC =
19109 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19113 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19121 SDValue SetCC =
19122 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
19126 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19327 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
20095 case ISD::SETCC: return LowerSETCC(Op, DAG);
20350 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
20437 case X86ISD::SETCC: return "X86ISD::SETCC";
22551 case X86ISD::SETCC:
23976 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
24147 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
24169 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
24244 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
24265 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
24337 Cond.getOpcode() == ISD::SETCC &&
24338 // Check if SETCC has already been promoted
24480 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
24484 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
24485 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
24488 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
24489 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
24505 // an SetCC or extended from it.
24509 SDValue SetCC;
24515 SetCC = Op2;
24517 SetCC = Op1;
24530 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24531 SetCC.getOpcode() == ISD::TRUNCATE ||
24532 SetCC.getOpcode() == ISD::AND) {
24533 if (SetCC.getOpcode() == ISD::AND) {
24535 if (isOneConstant(SetCC.getOperand(0)))
24537 if (isOneConstant(SetCC.getOperand(1)))
24541 SetCC = SetCC.getOperand(OpIdx);
24544 SetCC = SetCC.getOperand(0);
24547 switch (SetCC.getOpcode()) {
24555 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24558 case X86ISD::SETCC:
24560 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24563 return SetCC.getOperand(1);
24566 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24567 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24573 SDValue Op = SetCC.getOperand(0);
24598 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24601 return SetCC.getOperand(3);
24638 // Make sure we have SETCC nodes, using the same flags value.
24639 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24640 SetCC1.getOpcode() != X86ISD::SETCC ||
24700 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24704 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24718 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24721 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24759 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24819 // Fold and/or of setcc's to double CMOV:
25113 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
25735 // SetCC on x86 zero extends so only act on this if it's a logical shift.
27152 // ISD::SETCC is always legalized to i8.
27323 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
27357 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
27398 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
27537 SDValue SetCC = Ext.getOperand(0);
27538 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
27541 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
27545 SDValue Cmp = SetCC.getOperand(1);
27726 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
27727 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
