Lines Matching refs:Static
65 static cl::opt<bool> ExperimentalVectorWideningLegalization(
1912 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
2185 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2446 static StructReturnType
2460 static StructReturnType
2476 static SDValue
2489 static bool canGuaranteeTCO(CallingConv::ID CC) {
2495 static bool mayTailCallThisCC(CallingConv::ID CC) {
2514 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2602 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2607 static const MCPhysReg GPR64ArgRegsWin64[] = {
2613 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2620 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2642 static const MCPhysReg XMMArgRegs64Bit[] = {
3018 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
3038 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
3293 static const MCPhysReg XMMArgRegs[] = {
3406 // has hidden or protected visibility, or if it is static or local, then
3617 static
3888 static bool MayFoldLoad(SDValue Op) {
3892 static bool MayFoldIntoStore(SDValue Op) {
3896 static bool isTargetShuffle(unsigned Opcode) {
3927 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3942 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
4028 static bool isX86CCUnsigned(unsigned X86CC) {
4044 static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
4063 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
4139 static bool hasFPCMov(unsigned X86CC) {
4210 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4219 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4224 static bool isUndefOrEqual(int Val, int CmpVal) {
4231 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4241 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4260 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4291 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4306 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4353 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4385 static SDValue getZeroVector(MVT VT, const X86Subtarget *Subtarget,
4432 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4470 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4478 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4484 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4514 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4563 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4570 static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
4648 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4655 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4666 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4693 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4705 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4720 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4741 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5024 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5087 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5157 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5188 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5294 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5307 static SDValue
5390 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5501 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5661 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5691 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5763 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5878 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5992 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6032 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
6134 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
6614 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6638 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6715 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6751 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6766 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6778 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6798 static bool
6833 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6866 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6890 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6928 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6965 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
7008 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
7040 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7203 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7237 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7287 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7423 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7491 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7630 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7788 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7908 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7936 static bool isShuffleFoldableLoad(SDValue V) {
7947 static SDValue lowerVectorShuffleAsElementInsertion(
8050 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
8105 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
8206 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8287 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8401 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8482 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8592 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8611 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8701 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8780 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8896 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
9331 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9394 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9531 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9585 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9878 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9909 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9960 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10091 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
10150 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10195 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10288 static SDValue lowerVectorShuffleByMerging128BitLanes(
10364 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10374 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10409 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10491 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10570 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10662 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10741 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10832 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10909 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10967 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
11001 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
11018 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11040 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11058 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11080 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11098 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11113 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11133 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11181 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11238 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11373 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11418 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11487 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11844 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11875 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11901 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12116 // A direct static reference to a global.
12158 static SDValue
12190 static SDValue
12204 static SDValue
12211 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12251 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12459 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12637 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12733 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13161 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13207 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13233 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13242 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13323 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13337 static const int ShufMask[] = {0, 2, 4, 6};
13363 static const int ShufMask[] = {0, 2, -1, -1};
13381 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13392 static const int ShufMask2[] = {0, 1, 4, 5};
13456 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13471 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13548 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13637 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13649 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13741 static bool hasNonFlagsUse(SDValue Op) {
14199 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14244 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14272 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14315 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14358 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14385 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14618 static const int MaskHi[] = { 1, 1, 3, 3 };
14619 static const int MaskLo[] = { 0, 0, 2, 2 };
14646 static const int Mask[] = { 1, 0, 3, 2 };
14771 static bool isX86LogicalCmp(SDValue Op) {
14796 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15088 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
15138 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
15194 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15252 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15435 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15447 static bool isXor1OfSetCC(SDValue Op) {
15947 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15972 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16049 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16102 static SDValue getMaskNode(SDValue Mask, MVT MaskVT,
16148 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16193 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16216 static int getSEHRegistrationNodeSize(const Function *Fn) {
16239 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16277 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16949 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16983 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17013 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17037 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17083 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17134 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17143 static SDValue MarkEHRegistrationNode(SDValue Op, SelectionDAG &DAG) {
17154 report_fatal_error("llvm.x86.seh.ehregnode expects a static alloca");
17163 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
17198 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17524 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17756 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17807 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17846 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17876 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17924 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17951 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17961 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17971 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17978 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18072 static const int UnpackMask[] = { 1, -1, 3, -1 };
18086 static const int ShufMask[] = { 0, 4, 2, 6 };
18184 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18261 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18280 static
18288 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18306 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18475 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18558 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
19017 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
19051 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
19196 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19262 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19295 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19337 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19393 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19458 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19518 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19589 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19619 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19626 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19641 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19666 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19692 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19747 static SDValue ExtendToType(SDValue InOp, MVT NVT, SelectionDAG &DAG,
19796 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19890 static SDValue LowerMLOAD(SDValue Op, const X86Subtarget *Subtarget,
19922 static SDValue LowerMSTORE(SDValue Op, const X86Subtarget *Subtarget,
19946 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
20673 if ((M != CodeModel::Small || R != Reloc::Static) &&
20855 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20912 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20949 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20984 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
21343 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
21377 static bool isCMOVPseudo(MachineInstr *MI) {
22049 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
22616 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22632 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22646 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22749 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22959 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
23080 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
23122 static SDValue
23257 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
23320 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
23462 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
23516 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
23627 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23720 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23768 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23914 static SDValue
23960 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
24494 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
24612 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24651 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24863 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24949 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
25009 static SDValue PerformSRACombine(SDNode *N, SelectionDAG &DAG) {
25065 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
25094 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
25116 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
25218 static bool CanFoldXORWithAllOnes(const SDNode *N) {
25250 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
25329 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
25422 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
25454 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
25520 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
25682 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25719 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25761 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25783 static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
25901 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25953 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
26033 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
26122 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
26402 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
26514 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
26529 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
26544 static SDValue
26601 static SDValue
26631 static SDValue combineVectorTruncation(SDNode *N, SelectionDAG &DAG,
26689 static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
26701 static SDValue PerformFNEGCombine(SDNode *N, SelectionDAG &DAG,
26743 static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
26769 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
26787 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
26807 static SDValue performFMaxNumCombine(SDNode *N, SelectionDAG &DAG,
26858 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG,
26874 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG,
26889 static SDValue PerformBTCombine(SDNode *N,
26908 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
26921 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
26960 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
27007 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
27107 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
27146 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
27206 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
27265 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
27291 static SDValue PerformGatherScatterCombine(SDNode *N, SelectionDAG &DAG) {
27308 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
27324 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
27365 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
27383 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
27429 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
27454 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
27500 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
27529 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
27567 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
27582 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
27616 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
27856 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
27874 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
