Lines Matching refs:V2
3039 SDValue V2) {
3045 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3943 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3955 return DAG.getNode(Opc, dl, VT, V1, V2);
4648 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4652 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4655 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4659 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4694 SDValue V2) {
4701 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4706 SDValue V2) {
4713 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4717 /// This produces a shuffle where the low element of V2 is swizzled into the
4720 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4724 MVT VT = V2.getSimpleValueType();
4726 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4730 // If this is the insertion idx, put the low elt of V2 here.
4732 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5256 SDValue V2 = Elt.getOperand(0);
5279 if (V2.getSimpleValueType() != MVT::v4f32)
5280 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5288 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
6485 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6487 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6622 SDValue V2 = Op.getOperand(1);
6625 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6632 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6635 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6683 SDValue V2 = Op.getOperand(1);
6685 assert(V1.getValueType() == V2.getValueType() &&
6693 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6699 if (V2.isUndef())
6706 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6709 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
6712 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
6797 /// entries from both V1 and V2 inputs to the wider mask.
6833 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6843 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6891 SDValue V1, SDValue V2) {
6896 while (V2.getOpcode() == ISD::BITCAST)
6897 V2 = V2->getOperand(0);
6900 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6912 SDValue V = M < Size ? V1 : V2;
6929 SDValue V1, SDValue V2,
6944 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6945 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6946 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6947 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6951 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6952 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6955 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6956 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6966 SDValue V2, ArrayRef<int> Mask,
6979 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6987 V = Mask[i] < Size ? V1 : V2;
6988 else if (V != (Mask[i] < Size ? V1 : V2))
7009 SDValue V2, ArrayRef<int> Mask,
7026 // We have to cast V2 around.
7028 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
7030 DAG.getBitcast(MaskVT, V2)));
7031 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
7041 SDValue V2, ArrayRef<int> Original,
7045 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7047 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7084 V2 = getZeroVector(VT, Subtarget, DAG, DL);
7100 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7117 V2 = DAG.getBitcast(BlendVT, V2);
7119 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7129 V2 = DAG.getBitcast(MVT::v8i16, V2);
7131 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7145 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7156 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
7186 V2 = DAG.getBitcast(BlendVT, V2);
7190 V1, V2));
7204 SDValue V2,
7226 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7239 SDValue V2,
7242 // Shuffle the input elements into the desired positions in V1 and V2 and
7263 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7267 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7268 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7283 /// Essentially it concatenates V1 and V2, shifts right by some number of
7288 SDValue V2,
7337 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7424 SDValue V2, ArrayRef<int> Mask,
7426 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7482 for (SDValue V : {V1, V2})
7492 SDValue V2, ArrayRef<int> Mask,
7494 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7523 SDValue &V = (M < Size ? V1 : V2);
7566 Base = V2;
7581 Insert = V2;
7592 } else if ((!Base || (Base == V2)) &&
7595 Base = V2;
7789 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7791 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7824 SDValue V = M < NumElements ? V1 : V2;
7891 return V2;
7948 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7950 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7969 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7984 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
8013 ExtVT, V1, V2);
8020 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8022 V2 = DAG.getBitcast(VT, V2);
8032 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8034 V2 = DAG.getBitcast(MVT::v2i64, V2);
8035 V2 = DAG.getNode(
8036 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8040 V2 = DAG.getBitcast(VT, V2);
8043 return V2;
8204 // perform INSERTPS if a single V1 element is out of place and all V2
8206 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8211 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8214 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8242 // V2 input for insertion.
8255 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8256 // and don't use the original V2 at all.
8259 V2 = V1;
8265 // the zero mask and the V2 insertion - so remove V1 dependency.
8272 // Insert the V2 element into the desired position.
8274 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8288 SDValue V1, SDValue V2,
8338 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8342 V2 = DAG.getBitcast(UnpackVT, V2);
8347 UnpackVT, V1, V2));
8387 DL, VT, V1, V2),
8401 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8407 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8410 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8415 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8438 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8440 // Try inverting the insertion since for v2 masks it is easy to do and we
8445 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8451 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8452 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8458 DL, MVT::v2f64, V2,
8462 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8468 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8472 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8482 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8488 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8491 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8511 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8512 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8514 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8527 if (SDValue V2Pack = GetPackNode(V2))
8537 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8543 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8545 // Try inverting the insertion since for v2 masks it is easy to do and we
8549 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8556 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8562 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8569 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8575 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8583 V2 = DAG.getBitcast(MVT::v2f64, V2);
8585 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8613 SDValue V2, SelectionDAG &DAG) {
8614 SDValue LowV = V1, HighV = V2;
8630 // Handles all the cases where we have a single V2 element and an undef.
8637 // Handle the case where the V2 element ends up adjacent to a V1 element.
8641 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8647 LowV = V2;
8650 HighV = V2;
8652 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8653 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8657 // Handle the easy case where we have V1 in the low lanes and V2 in the
8668 LowV = V2;
8670 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8675 // V2.
8680 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8701 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8707 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8723 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8725 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8745 // when the V2 input is targeting element 0 of the mask -- that is the fast
8748 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8753 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8758 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8763 DL, MVT::v4f32, V1, V2, Mask, DAG))
8769 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8773 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8780 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8786 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8794 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8814 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8816 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8825 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8830 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8838 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8843 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8848 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8855 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8861 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8866 V2, Mask, DAG))
8877 DAG.getBitcast(MVT::v4f32, V2), Mask));
9332 SDValue V2, ArrayRef<int> Mask,
9335 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9367 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9368 DAG.getBitcast(MVT::v16i8, V2),
9374 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9376 V = V1InUse ? V1 : V2;
9394 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9400 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9412 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9434 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9452 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9457 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9462 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9470 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9475 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9480 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9485 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9489 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9493 V2, Mask, DAG))
9500 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9506 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9585 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9591 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9598 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9603 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9608 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9613 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9718 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9723 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9743 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9746 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9751 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9764 DL, MVT::v16i8, V1, V2, Mask, DAG))
9773 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9778 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9804 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9808 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9809 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9820 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9878 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9883 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9885 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9887 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9889 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9891 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9893 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9961 SDValue V2, ArrayRef<int> Mask,
9966 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
10012 std::tie(LoV2, HiV2) = SplitVector(V2);
10047 // First try just blending the halves of V1 or V2.
10070 // We only use half of V2 so map the usage down into the final blend mask.
10092 SDValue V2, ArrayRef<int> Mask,
10119 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10134 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10138 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10151 SDValue V1, SDValue V2,
10166 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10188 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10191 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10196 SDValue V2, ArrayRef<int> Mask,
10204 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10209 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10216 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10217 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10223 OnlyUsesV1 ? V1 : V2,
10254 // Shuffle mask values >= 4 are selecting elements of V2.
10265 V2 = DAG.getUNDEF(VT);
10272 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10289 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10341 V2 = DAG.getBitcast(LaneVT, V2);
10342 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10376 SDValue V2, SelectionDAG &DAG) {
10397 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10400 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10409 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10414 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10421 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10431 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10449 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10455 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10458 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10464 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10474 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10480 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10484 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10491 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10496 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10504 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10507 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10543 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10548 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10558 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10562 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10570 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10575 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10580 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10597 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10599 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10608 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10617 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10638 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10645 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10651 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10655 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10662 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10667 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10676 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10680 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10701 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10707 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10711 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10729 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10733 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10741 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10746 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10755 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10764 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10770 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10775 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10780 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10787 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10821 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10825 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10832 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10837 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10846 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10855 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10861 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10866 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10871 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10878 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10897 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10901 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10909 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10925 DL, VT, V1, V2, Mask, Subtarget, DAG))
10938 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10943 V2 = DAG.getBitcast(FpVT, V2);
10944 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10949 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10951 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10953 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10955 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10957 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10959 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10969 SDValue V1, SDValue V2,
10997 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
11003 SDValue V2, SelectionDAG &DAG) {
11014 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
11018 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11023 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
11029 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
11033 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
11036 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
11040 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11045 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
11051 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
11054 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
11058 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11063 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
11069 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
11073 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
11076 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
11080 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11085 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11091 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
11094 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
11098 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11103 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11109 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
11113 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11118 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11125 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
11133 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11153 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11155 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11157 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11159 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11162 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11166 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11174 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11181 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11220 if (V2.isUndef())
11221 V2 = DAG.getUNDEF(ExtVT);
11222 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11223 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11224 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11225 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11227 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11229 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11243 SDValue V2 = Op.getOperand(1);
11253 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11273 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11279 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11298 V2 = DAG.getBitcast(NewVT, V2);
11300 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11314 // V2. This allows us to match the shuffle pattern strictly on how many
11319 // When the number of V1 and V2 elements are the same, try to minimize the
11320 // number of uses of V2 in the low half of the vector. When that is tied,
11322 // indices for V2. When those are equal, try to ensure that the number of odd
11323 // indices for V1 is lower than the number of odd indices for V2.
11357 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11360 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11363 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11366 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
18988 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
19008 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
19011 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
22652 SDValue V2 = SVOp->getOperand(1);
22657 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22668 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22669 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22673 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
23478 SDValue V2 = N->getOperand(1);
23482 if (V1.getOpcode() == ISD::FADD && V2.getOpcode() == ISD::FSUB) {
23484 std::swap(V1, V2);
23485 } else if (V1.getOpcode() != ISD::FSUB || V2.getOpcode() != ISD::FADD)
23489 if (!V1->hasOneUse() || !V2->hasOneUse())
23495 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
23496 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
23501 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
23502 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
23503 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
25234 SDValue V2 = N->getOperand(1);
25239 ISD::isBuildVectorAllOnes(V2.getNode()))
