Lines Matching refs:Index
271 // itinerary resources. Index reads and writes in separate domains.
463 // Index zero reserved for invalid RW.
494 SchedClasses.back().Index = 0;
558 ProcIndices.push_back(ProcModel.Index);
572 if (!std::count(ProcIndices.begin(), ProcIndices.end(), PI->Index))
593 // Get the SchedClass index for an instruction.
653 SC.Index = Idx;
724 SC.Index = SCIdx;
791 ProcModel.ItinDefList[SCI->Index] = ItinData;
836 assert(SchedClasses[Idx].Index == Idx && "bad SCIdx");
893 unsigned PIdx = getProcModel(Rec->getValueAsDef("SchedModel")).Index;
903 unsigned RWIdx; // Index of this variant or sequence's matched type.
904 unsigned ProcIdx; // Processor model index or zero for any.
905 unsigned TransVecIdx; // Index into PredTransitions::TransVec.
912 // RWIdx is the index of the read/write variant.
998 SchedModels.expandRWSequence(AliasRW.Index, ExpandedRWs, AliasRW.IsRead);
1052 VarProcIdx = SchedModels.getProcModel(ModelDef).Index;
1057 Variants.push_back(TransVariant(*RI, SchedRW.Index, VarProcIdx, 0));
1069 AliasProcIdx = SchedModels.getProcModel(ModelDef).Index;
1077 Variants.push_back(TransVariant(*RI, AliasRW.Index, AliasProcIdx, 0));
1081 TransVariant(AliasRW.TheDef, SchedRW.Index, AliasProcIdx, 0));
1089 // A zero processor index means any processor.
1198 // operand. StartIdx is an index into TransVec where partial results
1443 IdxVec ProcIndices(1, getProcModel(RWModelDef).Index);
1457 addWriteRes(*WRI, getProcModel(ModelDef).Index);
1462 addWriteRes(*WRI, getProcModel(ModelDef).Index);
1467 addReadAdvance(*RAI, getProcModel(ModelDef).Index);
1473 addReadAdvance(*RAI, getProcModel(ModelDef).Index);
1567 getProcModel((*AI)->getValueAsDef("SchedModel")).Index);
1575 expandRWSequence(AliasRW.Index, ExpandedRWs, IsRead);
1704 dbgs() << Index << ": " << ModelName << " "
1719 dbgs() << "SCHEDCLASS " << Index << ":" << Name << '\n'
