Lines Matching defs:surf
65 gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling)
69 surf->ss0.tiled_surface = 0;
70 surf->ss0.tile_walk = 0;
73 surf->ss0.tiled_surface = 1;
74 surf->ss0.tile_walk = BRW_TILEWALK_XMAJOR;
77 surf->ss0.tiled_surface = 1;
78 surf->ss0.tile_walk = BRW_TILEWALK_YMAJOR;
85 gen7_set_surface_msaa(struct gen7_surface_state *surf, unsigned num_samples,
89 surf->ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_8;
91 surf->ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_4;
93 surf->ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_1;
95 surf->ss4.multisampled_surface_storage_format =
104 struct gen7_surface_state *surf,
128 surf->ss6.mcs_enabled.mcs_enable = 1;
129 surf->ss6.mcs_enabled.mcs_surface_pitch = pitch_tiles - 1;
130 surf->ss6.mcs_enabled.mcs_base_address = mcs_mt->region->bo->offset >> 12;
135 surf->ss6.raw_data & 0xfff,
143 gen7_check_surface_setup(struct gen7_surface_state *surf,
147 surf->ss4.num_multisamples != GEN7_SURFACE_MULTISAMPLECOUNT_1;
156 if (surf->ss4.multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS
158 assert(surf->ss0.surface_array_spacing == GEN7_SURFACE_ARYSPC_LOD0);
172 assert(surf->ss4.multisampled_surface_storage_format ==
184 if (surf->ss4.num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 &&
185 surf->ss2.width >= 8192) {
186 assert(surf->ss4.multisampled_surface_storage_format ==
206 uint32_t depth = surf->ss3.depth + 1;
207 uint32_t height = surf->ss2.height + 1;
208 if (surf->ss4.num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 &&
210 assert(surf->ss4.multisampled_surface_storage_format ==
213 if (surf->ss4.num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_4 &&
215 assert(surf->ss4.multisampled_surface_storage_format ==
219 switch (surf->ss0.surface_format) {
224 assert(surf->ss4.multisampled_surface_storage_format ==
239 struct gen7_surface_state *surf;
246 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
247 sizeof(*surf), 32, &binding_table[surf_index]);
248 memset(surf, 0, sizeof(*surf));
250 surf->ss0.surface_type = BRW_SURFACE_BUFFER;
251 surf->ss0.surface_format = brw_format_for_mesa_format(format);
253 surf->ss0.render_cache_read_write = 1;
255 if (surf->ss0.surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
261 surf->ss1.base_addr = bo->offset; /* reloc */
274 surf->ss2.width = w & 0x7f; /* bits 6:0 of size or width */
275 surf->ss2.height = (w >> 7) & 0x1fff; /* bits 19:7 of size or width */
276 surf->ss3.depth = (w >> 20) & 0x7f; /* bits 26:20 of size or width */
277 surf->ss3.pitch = texel_size - 1;
279 surf->ss1.base_addr = 0;
280 surf->ss2.width = 0;
281 surf->ss2.height = 0;
282 surf->ss3.depth = 0;
283 surf->ss3.pitch = 0;
286 gen7_set_surface_tiling(surf, I915_TILING_NONE);
288 gen7_check_surface_setup(surf, false /* is_render_target */);
303 struct gen7_surface_state *surf;
317 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
318 sizeof(*surf), 32, &binding_table[surf_index]);
319 memset(surf, 0, sizeof(*surf));
322 surf->ss0.vertical_alignment = 1;
324 surf->ss0.horizontal_alignment = 1;
326 surf->ss0.surface_type = translate_tex_target(tObj->Target);
327 surf->ss0.surface_format = translate_tex_format(mt->format,
332 surf->ss0.cube_pos_x = 1;
333 surf->ss0.cube_pos_y = 1;
334 surf->ss0.cube_pos_z = 1;
335 surf->ss0.cube_neg_x = 1;
336 surf->ss0.cube_neg_y = 1;
337 surf->ss0.cube_neg_z = 1;
340 surf->ss0.is_array = depth > 1 && tObj->Target != GL_TEXTURE_3D;
342 gen7_set_surface_tiling(surf, intelObj->mt->region->tiling);
351 surf->ss1.base_addr =
354 surf->ss2.width = width - 1;
355 surf->ss2.height = height - 1;
357 surf->ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1;
358 surf->ss3.depth = depth - 1;
362 surf->ss5.mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
363 surf->ss5.min_lod = 0;
383 surf->ss7.shader_channel_select_r = swizzle_to_scs(GET_SWZ(swizzle, 0));
384 surf->ss7.shader_channel_select_g = swizzle_to_scs(GET_SWZ(swizzle, 1));
385 surf->ss7.shader_channel_select_b = swizzle_to_scs(GET_SWZ(swizzle, 2));
386 surf->ss7.shader_channel_select_a = swizzle_to_scs(GET_SWZ(swizzle, 3));
396 gen7_check_surface_setup(surf, false /* is_render_target */);
411 struct gen7_surface_state *surf;
413 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
414 sizeof(*surf), 32, out_offset);
415 memset(surf, 0, sizeof(*surf));
417 surf->ss0.surface_type = BRW_SURFACE_BUFFER;
418 surf->ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
420 surf->ss0.render_cache_read_write = 1;
423 surf->ss1.base_addr = bo->offset + offset; /* reloc */
425 surf->ss2.width = w & 0x7f; /* bits 6:0 of size or width */
426 surf->ss2.height = (w >> 7) & 0x1fff; /* bits 19:7 of size or width */
427 surf->ss3.depth = (w >> 20) & 0x7f; /* bits 26:20 of size or width */
428 surf->ss3.pitch = (16 - 1); /* stride between samples */
429 gen7_set_surface_tiling(surf, I915_TILING_NONE); /* tiling now allowed */
432 surf->ss7.shader_channel_select_r = HSW_SCS_RED;
433 surf->ss7.shader_channel_select_g = HSW_SCS_GREEN;
434 surf->ss7.shader_channel_select_b = HSW_SCS_BLUE;
435 surf->ss7.shader_channel_select_a = HSW_SCS_ALPHA;
448 gen7_check_surface_setup(surf
471 struct gen7_surface_state *surf;
476 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
477 sizeof(*surf), 32, &brw->wm.surf_offset[unit]);
478 memset(surf, 0, sizeof(*surf));
480 surf->ss0.surface_type = BRW_SURFACE_NULL;
481 surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
483 surf->ss2.width = fb->Width - 1;
484 surf->ss2.height = fb->Height - 1;
490 gen7_set_surface_tiling(surf, I915_TILING_Y);
492 gen7_check_surface_setup(surf, true /* is_render_target */);
509 struct gen7_surface_state *surf;
513 surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
514 sizeof(*surf), 32, &brw->wm.surf_offset[unit]);
515 memset(surf, 0, sizeof(*surf));
521 surf->ss0.vertical_alignment = 1;
523 surf->ss0.horizontal_alignment = 1;
533 surf->ss0.surface_format = brw_format_for_mesa_format(rb_format);
535 surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
539 surf->ss0.surface_format = brw->render_target_format[rb_format];
547 surf->ss0.surface_type = BRW_SURFACE_2D;
548 surf->ss0.surface_array_spacing = irb->mt->array_spacing_lod0 ?
552 surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
553 surf->ss1.base_addr += region->bo->offset; /* reloc */
561 surf->ss5.x_offset = tile_x / 4;
562 surf->ss5.y_offset = tile_y / 2;
564 surf->ss2.width = rb->Width - 1;
565 surf->ss2.height = rb->Height - 1;
566 gen7_set_surface_tiling(surf, region->tiling);
567 surf->ss3.pitch = (region->pitch * region->cpp) - 1;
569 gen7_set_surface_msaa(surf, irb->mt->num_samples, irb->mt->msaa_layout);
572 gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[unit],
577 surf->ss7.shader_channel_select_r = HSW_SCS_RED;
578 surf->ss7.shader_channel_select_g = HSW_SCS_GREEN;
579 surf->ss7.shader_channel_select_b = HSW_SCS_BLUE;
580 surf->ss7.shader_channel_select_a = HSW_SCS_ALPHA;
587 surf->ss1.base_addr - region->bo->offset,
591 gen7_check_surface_setup(surf, true /* is_render_target */);
