Lines Matching refs:rmesa
105 #define LOCAL_VARS r200ContextPtr rmesa = R200_CONTEXT(ctx)
124 R200_STATECHANGE( rmesa, lin ); \
125 radeonEmitState(&rmesa->radeon); \
129 R200_STATECHANGE( rmesa, lin ); \
131 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
134 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
136 radeonEmitState(&rmesa->radeon); \
140 #define ALLOC_ELTS(nr) r200AllocElts( rmesa, nr )
142 static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr )
144 if (rmesa->radeon.dma.flush == r200FlushElts &&
145 rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) {
147 GLushort *dest = (GLushort *)(rmesa->radeon.tcl.elt_dma_bo->ptr +
148 rmesa->radeon.tcl.elt_dma_offset + rmesa->tcl.elt_used);
150 rmesa->tcl.elt_used += nr*2;
155 if (rmesa->radeon.dma.flush)
156 rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
158 r200EmitAOS( rmesa,
159 rmesa->radeon.tcl.aos_count, 0 );
161 r200EmitMaxVtxIndex(rmesa, rmesa->radeon.tcl.aos[0].count);
162 return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr );
169 if (0) R200_NEWPRIM( rmesa ); \
184 r200ContextPtr rmesa = R200_CONTEXT( ctx );
187 // fprintf(stderr,"Emit prim %d\n", rmesa->radeon.tcl.aos_count);
189 r200EmitAOS( rmesa,
190 rmesa->radeon.tcl.aos_count,
195 r200EmitVbufPrim( rmesa,
196 rmesa->tcl.hw_primitive,
202 (void) rmesa; } while (0)
213 rmesa->tcl.hw_primitive == (PRIM| \
224 (void)rmesa; } while (0)
228 (void)rmesa; } while (0)
262 r200ContextPtr rmesa = R200_CONTEXT(ctx);
265 radeon_prepare_render(&rmesa->radeon);
266 if (rmesa->radeon.NewGLState)
269 if (newprim != rmesa->tcl.hw_primitive ||
273 if (rmesa->hw.set.cmd[SET_RE_CNTL] & R200_PERSPECTIVE_ENABLE) {
274 R200_STATECHANGE( rmesa, set );
275 rmesa->hw.set.cmd[SET_RE_CNTL] &= ~R200_PERSPECTIVE_ENABLE;
278 else if (!(rmesa->hw.set.cmd[SET_RE_CNTL] & R200_PERSPECTIVE_ENABLE)) {
279 R200_STATECHANGE( rmesa, set );
280 rmesa->hw.set.cmd[SET_RE_CNTL] |= R200_PERSPECTIVE_ENABLE;
282 R200_NEWPRIM( rmesa );
283 rmesa->tcl.hw_primitive = newprim;
293 r200ContextPtr rmesa = R200_CONTEXT(ctx);
312 state_size = radeonCountStateEmitSize( &rmesa->radeon );
314 if (!rmesa->hw.vtx.dirty)
315 state_size += rmesa->hw.vtx.check(rmesa->radeon.glCtx, &rmesa->hw.vtx);
342 if (rcommonEnsureCmdBufSpace(&rmesa->radeon, space_required + state_size, __FUNCTION__))
343 return space_required + radeonCountStateEmitSize( &rmesa->radeon );
359 r200ContextPtr rmesa = R200_CONTEXT(ctx);
373 if (rmesa->radeon.TclFallback)
383 if (rmesa->radeon.NewGLState)
415 if (rmesa->TexGenNeedNormals[i]) {
431 rmesa->curr_vp_hw->mesa_program.Base.OutputsWritten;
433 vimap_rev = &rmesa->curr_vp_hw->inputmap_rev[0];
453 if (rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] != out_compsel) {
454 R200_STATECHANGE( rmesa, vtx );
455 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = out_compsel;
463 + rmesa->radeon.cmdbuf.cs->cdw;
480 if ( emit_end < rmesa->radeon.cmdbuf.cs->cdw )
482 " We might overflow command buffer.\n", rmesa->radeon.cmdbuf.cs->cdw - emit_end);
515 r200ContextPtr rmesa = R200_CONTEXT(ctx);
518 R200_NEWPRIM( rmesa );
533 R200_STATECHANGE( rmesa, vap );
534 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] &= ~(R200_VAP_TCL_ENABLE|R200_VAP_PROG_VTX_SHADER_ENABLE);
539 r200ContextPtr rmesa = R200_CONTEXT(ctx);
548 if ( rmesa->radeon.dma.flush )
549 rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
551 rmesa->radeon.dma.flush = NULL;
553 R200_STATECHANGE( rmesa, vap );
554 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_TCL_ENABLE;
555 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] &= ~R200_VAP_FORCE_W_TO_ONE;
558 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_PROG_VTX_SHADER_ENABLE;
561 if ( ((rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] & R200_FOG_USE_MASK)
564 R200_STATECHANGE( rmesa, ctx );
565 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] &= ~R200_FOG_USE_MASK;
566 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] |= R200_FOG_USE_VTX_FOG;
569 R200_STATECHANGE( rmesa, vte );
570 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] &= ~(R200_VTX_XY_FMT|R200_VTX_Z_FMT);
571 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] |= R200_VTX_W0_FMT;
609 r200ContextPtr rmesa = R200_CONTEXT(ctx);
610 GLuint oldfallback = rmesa->radeon.TclFallback;
615 if ( rmesa->radeon.dma.flush )
616 rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
621 rmesa->radeon.TclFallback |= bit;
624 rmesa->radeon.TclFallback |= bit;
628 if ( rmesa->radeon.dma.flush )
629 rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
634 rmesa->radeon.TclFallback &= ~bit;
637 rmesa->radeon.TclFallback &= ~bit;
