Lines Matching full:reg_map
45 static SLJIT_CONST sljit_ub reg_map[SLJIT_NUMBER_OF_REGISTERS + 6] = {
53 #define RD3(rd) (reg_map[rd])
54 #define RN3(rn) (reg_map[rn] << 3)
55 #define RM3(rm) (reg_map[rm] << 6)
56 #define RDN3(rdn) (reg_map[rdn] << 8)
62 ((reg_map[rn] << 3) | (reg_map[rd] & 0x7) | ((reg_map[rd] & 0x8) << 4))
64 (reg_map[reg1] <= 7 && reg_map[reg2] <= 7)
66 (reg_map[reg1] <= 7 && reg_map[reg2] <= 7 && reg_map[reg3] <= 7)
69 #define RD4(rd) (reg_map[rd] << 8)
70 #define RN4(rn) (reg_map[rn] << 16)
71 #define RM4(rm) (reg_map[rm])
72 #define RT4(rt) (reg_map[rt] << 12)
724 if (reg_map[dst] <= 7)
750 SLJIT_ASSERT(reg_map[TMP_REG2] <= 7 && dst != TMP_REG2);
963 if (SLJIT_UNLIKELY(arg == SLJIT_SP) && OFFSET_CHECK(0xff, 2) && IS_WORD_SIZE(flags) && reg_map[reg] <= 7) {
1145 push |= 1 << reg_map[i];
1148 push |= 1 << reg_map[i];
1211 pop |= 1 << reg_map[i];
1214 pop |= 1 << reg_map[i];
1257 | (reg_map[SLJIT_R1] << 8)
1258 | (reg_map[SLJIT_R0] << 12)
1259 | (reg_map[SLJIT_R0] << 16)
1260 | reg_map[SLJIT_R1]);
1266 SLJIT_COMPILE_ASSERT(reg_map[2] == 1 && reg_map[3] == 2 && reg_map[4] == 12, bad_register_mapping);
1529 return reg_map[reg];
1997 if (reg_map[dst_r] > 7) {
2016 if (reg_map[dst] <= 7)
2050 if (reg_map[dst_r] <= 7)
