Lines Matching refs:Operand
257 // Implementation of Operand and MemOperand
260 Operand::Operand(Handle<Object> handle) {
277 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
298 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
848 patcher.masm()->mov(dst, Operand(target24));
872 patcher.masm()->mov(dst, Operand(target8_0));
873 patcher.masm()->orr(dst, dst, Operand(target8_1 << 8));
877 patcher.masm()->mov(dst, Operand(target8_0));
878 patcher.masm()->orr(dst, dst, Operand(target8_1 << 8));
879 patcher.masm()->orr(dst, dst, Operand(target8_2 << 16));
1059 bool Operand::must_output_reloc_info(const Assembler* assembler) const {
1070 static bool use_mov_immediate_load(const Operand& x,
1089 int Operand::instructions_required(const Assembler* assembler,
1095 // The immediate operand cannot be encoded as a shifter operand, or use of
1119 // No use of constant pool and the immediate operand can be encoded as a
1120 // shifter operand.
1127 const Operand& x,
1146 mov(target, Operand(imm32 & kImm8Mask), LeaveCC, cond);
1147 orr(target, target, Operand(imm32 & (kImm8Mask << 8)), LeaveCC, cond);
1148 orr(target, target, Operand(imm32 & (kImm8Mask << 16)), LeaveCC, cond);
1149 orr(target, target, Operand(imm32 & (kImm8Mask << 24)), LeaveCC, cond);
1166 mov(target, Operand(0), LeaveCC, cond);
1167 orr(target, target, Operand(0), LeaveCC, cond);
1168 orr(target, target, Operand(0), LeaveCC, cond);
1169 orr(target, target, Operand(0), LeaveCC, cond);
1185 const Operand& x) {
1194 // The immediate operand cannot be encoded as a shifter operand, so load
1204 addrmod1(instr, rn, rd, Operand(ip));
1239 mov(ip, Operand(x.offset_), LeaveCC, Instruction::ConditionField(instr));
1272 mov(ip, Operand(x.offset_), LeaveCC, Instruction::ConditionField(instr));
1282 mov(ip, Operand(x.rm_, x.shift_op_, x.shift_imm_), LeaveCC,
1419 void Assembler::and_(Register dst, Register src1, const Operand& src2,
1425 void Assembler::eor(Register dst, Register src1, const Operand& src2,
1431 void Assembler::sub(Register dst, Register src1, const Operand& src2,
1437 void Assembler::rsb(Register dst, Register src1, const Operand& src2,
1443 void Assembler::add(Register dst, Register src1, const Operand& src2,
1449 void Assembler::adc(Register dst, Register src1, const Operand& src2,
1455 void Assembler::sbc(Register dst, Register src1, const Operand& src2,
1461 void Assembler::rsc(Register dst, Register src1, const Operand& src2,
1467 void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
1472 void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
1477 void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
1489 void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
1494 void Assembler::orr(Register dst, Register src1, const Operand& src2,
1500 void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) {
1514 mov(dst, Operand(label->pos() + (Code::kHeaderSize - kHeapObjectTag)));
1563 void Assembler::bic(Register dst, Register src1, const Operand& src2,
1569 void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) {
1700 const Operand& src,
1797 const Operand& src2,
1816 const Operand& src2,
1957 void Assembler::msr(SRegisterFieldMask fields, const Operand& src,
1967 // Immediate operand cannot be encoded, load it first to register ip.
1969 msr(fields, Operand(ip), cond);
2275 add(ip, base, Operand(offset));
2277 sub(ip, base, Operand(offset));
2285 const MemOperand& operand,
2287 DCHECK(operand.am_ == Offset);
2288 if (operand.rm().is_valid()) {
2289 add(ip, operand.rn(),
2290 Operand(operand.rm(), operand.shift_op_, operand.shift_imm_));
2293 vldr(dst, operand.rn(), operand.offset(), cond);
2323 add(ip, base, Operand(offset));
2325 sub(ip, base, Operand(offset));
2333 const MemOperand& operand,
2335 DCHECK(operand.am_ == Offset);
2336 if (operand.rm().is_valid()) {
2337 add(ip, operand.rn(),
2338 Operand(operand.rm(), operand.shift_op_, operand.shift_imm_));
2341 vldr(dst, operand.rn(), operand.offset(), cond);
2372 add(ip, base, Operand(offset));
2374 sub(ip, base, Operand(offset));
2382 const MemOperand& operand,
2384 DCHECK(operand.am_ == Offset);
2385 if (operand.rm().is_valid()) {
2386 add(ip, operand.rn(),
2387 Operand(operand.rm(), operand.shift_op_, operand.shift_imm_));
2390 vstr(src, operand.rn(), operand.offset(), cond);
2420 add(ip, base, Operand(offset));
2422 sub(ip, base, Operand(offset));
2430 const MemOperand& operand,
2432 DCHECK(operand.am_ == Offset);
2433 if (operand.rm().is_valid()) {
2434 add(ip, operand.rn(),
2435 Operand(operand.rm(), operand.shift_op_, operand.shift_imm_));
2438 vstr(src, operand.rn(), operand.offset(), cond);
2525 mov(ip, Operand(bit_cast<int32_t>(imm)));
2646 mov(ip, Operand(lo));
2649 mov(ip, Operand(lo));
2655 mov(ip, Operand(hi));
2661 mov(ip, Operand(lo));
2662 mov(scratch, Operand(hi));
