Lines Matching refs:Operand
280 bool Operand::NeedsRelocation(const Assembler* assembler) const {
1093 const Operand& operand) {
1094 AddSub(rd, rn, operand, LeaveFlags, ADD);
1100 const Operand& operand) {
1101 AddSub(rd, rn, operand, SetFlags, ADD);
1106 const Operand& operand) {
1108 adds(zr, rn, operand);
1114 const Operand& operand) {
1115 AddSub(rd, rn, operand, LeaveFlags, SUB);
1121 const Operand& operand) {
1122 AddSub(rd, rn, operand, SetFlags, SUB);
1126 void Assembler::cmp(const Register& rn, const Operand& operand) {
1128 subs(zr, rn, operand);
1132 void Assembler::neg(const Register& rd, const Operand& operand) {
1134 sub(rd, zr, operand);
1138 void Assembler::negs(const Register& rd, const Operand& operand) {
1140 subs(rd, zr, operand);
1146 const Operand& operand) {
1147 AddSubWithCarry(rd, rn, operand, LeaveFlags, ADC);
1153 const Operand& operand) {
1154 AddSubWithCarry(rd, rn, operand, SetFlags, ADC);
1160 const Operand& operand) {
1161 AddSubWithCarry(rd, rn, operand, LeaveFlags, SBC);
1167 const Operand& operand) {
1168 AddSubWithCarry(rd, rn, operand, SetFlags, SBC);
1172 void Assembler::ngc(const Register& rd, const Operand& operand) {
1174 sbc(rd, zr, operand);
1178 void Assembler::ngcs(const Register& rd, const Operand& operand) {
1180 sbcs(rd, zr, operand);
1187 const Operand& operand) {
1188 Logical(rd, rn, operand, AND);
1194 const Operand& operand) {
1195 Logical(rd, rn, operand, ANDS);
1200 const Operand& operand) {
1201 ands(AppropriateZeroRegFor(rn), rn, operand);
1207 const Operand& operand) {
1208 Logical(rd, rn, operand, BIC);
1214 const Operand& operand) {
1215 Logical(rd, rn, operand, BICS);
1221 const Operand& operand) {
1222 Logical(rd, rn, operand, ORR);
1228 const Operand& operand) {
1229 Logical(rd, rn, operand, ORN);
1235 const Operand& operand) {
1236 Logical(rd, rn, operand, EOR);
1242 const Operand& operand) {
1243 Logical(rd, rn, operand, EON);
1403 const Operand& operand,
1406 ConditionalCompare(rn, operand, nzcv, cond, CCMN);
1411 const Operand& operand,
1414 ConditionalCompare(rn, operand, nzcv, cond, CCMP);
1698 // second operand of zero. Otherwise, orr with first operand zr is
1708 void Assembler::mvn(const Register& rd, const Operand& operand) {
1709 orn(rd, AppropriateZeroRegFor(rd), operand);
2171 const Operand& operand,
2175 DCHECK(!operand.NeedsRelocation(this));
2176 if (operand.IsImmediate()) {
2177 int64_t immediate = operand.ImmediateValue();
2182 } else if (operand.IsShiftedRegister()) {
2183 DCHECK(operand.reg().SizeInBits() == rd.SizeInBits());
2184 DCHECK(operand.shift() != ROR);
2191 // or their 64-bit register equivalents, convert the operand from shifted to
2195 DataProcExtendedRegister(rd, rn, operand.ToExtendedRegister(), S,
2198 DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op);
2201 DCHECK(operand.IsExtendedRegister());
2202 DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op);
2209 const Operand& operand,
2213 DCHECK(rd.SizeInBits() == operand.reg().SizeInBits());
2214 DCHECK(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
2215 DCHECK(!operand.NeedsRelocation(this));
2216 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd));
2279 const Operand& operand,
2282 DCHECK(!operand.NeedsRelocation(this));
2283 if (operand.IsImmediate()) {
2284 int64_t immediate = operand.ImmediateValue();
2306 DCHECK(operand.IsShiftedRegister());
2307 DCHECK(operand.reg().SizeInBits() == rd.SizeInBits());
2309 DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op);
2329 const Operand& operand,
2334 DCHECK(!operand.NeedsRelocation(this));
2335 if (operand.IsImmediate()) {
2336 int64_t immediate = operand.ImmediateValue();
2341 DCHECK(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
2342 ccmpop = ConditionalCompareRegisterFixed | op | Rm(operand.reg());
2445 const Operand& operand,
2448 DCHECK(operand.IsShiftedRegister());
2449 DCHECK(rn.Is64Bits() || (rn.Is32Bits() && is_uint5(operand.shift_amount())));
2450 DCHECK(!operand.NeedsRelocation(this));
2452 ShiftDP(operand.shift()) | ImmDPShift(operand.shift_amount()) |
2453 Rm(operand.reg()) | Rn(rn) | Rd(rd));
2459 const Operand& operand,
2462 DCHECK(!operand.NeedsRelocation(this));
2464 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) |
2465 ExtendMode(operand.extend()) | ImmExtendShift(operand.shift_amount()) |
