Lines Matching refs:right
130 inputs[input_count++] = g.UseOperand(m.right().node(), operand_mode);
405 // Map instruction to equivalent operation with inverted right input.
421 if (mleft.right().Is(-1)) {
423 g.UseRegister(m->right().node()),
430 if ((m->right().IsWord32Xor() || m->right().IsWord64Xor()) &&
432 Matcher mright(m->right().node());
433 if (mright.right().Is(-1)) {
434 // TODO(all): support shifted operand on right.
472 // TODO(mbrandy): Absorb rotate-right into rlwinm?
478 if (m.right().HasValue() && IsContiguousMask32(m.right().Value(), &mb, &me)) {
483 // Try to absorb left/right shift into rlwinm
485 if (mleft.right().IsInRange(0, 31)) {
487 sh = mleft.right().Value();
506 CanCover(node, m.right().node()), kInt16Imm_Unsigned);
511 // TODO(mbrandy): Absorb rotate-right into rldic?
517 if (m.right().HasValue() && IsContiguousMask64(m.right().Value(), &mb, &me)) {
522 // Try to absorb left/right shift into rldic
524 if (mleft.right().IsInRange(0, 63)) {
526 sh = mleft.right().Value();
563 CanCover(node, m.right().node()), kInt16Imm_Unsigned);
572 CanCover(node, m.right().node()), kInt16Imm_Unsigned);
581 CanCover(node, m.right().node()), kInt16Imm_Unsigned);
589 if (m.right().Is(-1)) {
601 if (m.right().Is(-1)) {
613 if (m.left().IsWord32And() && m.right().IsInRange(0, 31)) {
616 int sh = m.right().Value();
619 if (mleft.right().HasValue() &&
620 IsContiguousMask32(mleft.right().Value() << sh, &mb, &me)) {
639 // TODO(mbrandy): eliminate left sign extension if right >= 32
640 if (m.left().IsWord64And() && m.right().IsInRange(0, 63)) {
643 int sh = m.right().Value();
646 if (mleft.right().HasValue() &&
647 IsContiguousMask64(mleft.right().Value() << sh, &mb, &me)) {
684 if (m.left().IsWord32And() && m.right().IsInRange(0, 31)) {
687 int sh = m.right().Value();
690 if (mleft.right().HasValue() &&
691 IsContiguousMask32((uint32_t)(mleft.right().Value()) >> sh, &mb, &me)) {
711 if (m.left().IsWord64And() && m.right().IsInRange(0, 63)) {
714 int sh = m.right().Value();
717 if (mleft.right().HasValue() &&
718 IsContiguousMask64((uint64_t)(mleft.right().Value()) >> sh, &mb, &me)) {
755 if (mleft.right().Is(16) && m.right().Is(16)) {
759 } else if (mleft.right().Is(24) && m.right().Is(24)) {
844 Emit(kPPC_Neg, g.DefineAsRegister(node), g.UseRegister(m.right().node()));
856 Emit(kPPC_Neg, g.DefineAsRegister(node), g.UseRegister(m.right().node()));
1081 g.UseRegister(m.right().node()));
1093 if (m.right().IsFloat64RoundDown() &&
1094 CanCover(m.node(), m.right().node())) {
1095 right().InputAt(0)->opcode() == IrOpcode::kFloat64Sub &&
1096 CanCover(m.right().node(), m.right().InputAt(0))) {
1097 Float64BinopMatcher mright0(m.right().InputAt(0));
1101 g.UseRegister(mright0.right().node()));
1107 g.UseRegister(m.right().node()));
1287 InstructionOperand left, InstructionOperand right,
1292 selector->Emit(opcode, g.NoOutput(), left, right,
1296 selector->Emit(opcode, g.DefineAsRegister(cont->result()), left, right);
1307 Node* right = node->InputAt(1);
1309 // Match immediates on left or right side of comparison.
1310 if (g.CanBeImmediate(right, immediate_mode)) {
1311 VisitCompare(selector, opcode, g.UseRegister(left), g.UseImmediate(right),
1315 VisitCompare(selector, opcode, g.UseRegister(right), g.UseImmediate(left),
1318 VisitCompare(selector, opcode, g.UseRegister(left), g.UseRegister(right),
1345 Node* right = node->InputAt(1);
1347 g.UseRegister(right), cont);
1356 Node* right = node->InputAt(1);
1358 g.UseRegister(right), cont);
1372 if (m.right().Is(0)) {
1563 if (m.right().Is(0)) {
1598 if (m.right().Is(0)) {
1726 Node* right = node->InputAt(1);
1731 g.UseRegister(right));
1735 g.UseRegister(left), g.UseRegister(right));
1742 Node* right = node->InputAt(1);
1746 Emit(kPPC_DoubleConstruct, g.DefineAsRegister(node), g.UseRegister(right),
1751 g.UseRegister(left), g.UseRegister(right));
