Lines Matching full:sbb
151 dis_op2_G_E (add, or, adc, sbb, and, sub, xor)
153 dis_Grp1 (add, or, adc, sbb, and, sub, xor)
2055 /* Given ta1, ta2 and tres, compute tres = SBB(ta1,ta2) and set flags
2119 = { "add", "or", "adc", "sbb", "and", "sub", "xor", "cmp" };
2948 vex_printf("vex amd64->IR: sbb %%r,%%r optimisation(1)\n");
3060 dependency. Ditto SBB reg,reg. */
3420 case 3: break; // SBB
3437 if (gregLO3ofRM(modrm) == 3 /* SBB */) {
3472 if (gregLO3ofRM(modrm) == 3 /* SBB */) {
9922 SBB 81 /3, 81 /3, 82 /x, 83 /3, 18, 19
9954 Same for ADD OR ADC SBB AND SUB XOR
19833 case 0x18: /* SBB Gb,Eb */ case 0x19: /* SBB Gv,Ev */
19934 case 0x18: /* SBB Gb,Eb */
19936 delta = dis_op2_G_E ( vbi, pfx, True, Iop_Sub8, True, 1, delta, "sbb" );
19938 case 0x19: /* SBB Gv,Ev */
19940 delta = dis_op2_G_E ( vbi, pfx, True, Iop_Sub8, True, sz, delta, "sbb" );
19943 case 0x1A: /* SBB Eb,Gb */
19945 delta = dis_op2_E_G ( vbi, pfx, True, Iop_Sub8, True, 1, delta, "sbb" );
19947 case 0x1B: /* SBB Ev,Gv */
19949 delta = dis_op2_E_G ( vbi, pfx, True, Iop_Sub8, True, sz, delta, "sbb" );
19952 case 0x1C: /* SBB Ib, AL */
19954 delta = dis_op_imm_A( 1, True, Iop_Sub8, True, delta, "sbb" );
19956 case 0x1D: /* SBB Iv, eAX */
19958 delta = dis_op_imm_A( sz, True, Iop_Sub8, True, delta, "sbb" );
