Lines Matching full:vex_state
1142 //ZZ /*OUT*/VexGuestARMState* vex_state )
1150 //ZZ vex_state->guest_CC_OP = ARMG_CC_OP_COPY;
1151 //ZZ vex_state->guest_CC_DEP1 = flags_native;
1152 //ZZ vex_state->guest_CC_DEP2 = 0;
1153 //ZZ vex_state->guest_CC_NDEP = 0;
1158 ULong LibVEX_GuestARM64_get_nzcv ( /*IN*/const VexGuestARM64State* vex_state )
1163 vex_state->guest_CC_OP,
1164 vex_state->guest_CC_DEP1,
1165 vex_state->guest_CC_DEP2,
1166 vex_state->guest_CC_NDEP
1170 //ZZ if (vex_state->guest_QFLAG32 > 0)
1173 //ZZ if (vex_state->guest_GEFLAG0 > 0)
1175 //ZZ if (vex_state->guest_GEFLAG1 > 0)
1177 //ZZ if (vex_state->guest_GEFLAG2 > 0)
1179 //ZZ if (vex_state->guest_GEFLAG3 > 0)
1185 //ZZ if (vex_state->guest_R15T & 1)
1196 ULong LibVEX_GuestARM64_get_fpsr ( const VexGuestARM64State* vex_state )
1198 UInt w32 = vex_state->guest_QCFLAG[0] | vex_state->guest_QCFLAG[1]
1199 | vex_state->guest_QCFLAG[2] | vex_state->guest_QCFLAG[3];
1207 void LibVEX_GuestARM64_set_fpsr ( /*MOD*/VexGuestARM64State* vex_state,
1211 vex_state->guest_QCFLAG[0] = (UInt)((fpsr >> 27) & 1);
1212 vex_state->guest_QCFLAG[1] = 0;
1213 vex_state->guest_QCFLAG[2] = 0;
1214 vex_state->guest_QCFLAG[3] = 0;
1218 void LibVEX_GuestARM64_initialise ( /*OUT*/VexGuestARM64State* vex_state )
1220 vex_bzero(vex_state, sizeof(*vex_state));
1221 //ZZ vex_state->host_EvC_FAILADDR = 0;
1222 //ZZ vex_state->host_EvC_COUNTER = 0;
1224 //ZZ vex_state->guest_R0 = 0;
1225 //ZZ vex_state->guest_R1 = 0;
1226 //ZZ vex_state->guest_R2 = 0;
1227 //ZZ vex_state->guest_R3 = 0;
1228 //ZZ vex_state->guest_R4 = 0;
1229 //ZZ vex_state->guest_R5 = 0;
1230 //ZZ vex_state->guest_R6 = 0;
1231 //ZZ vex_state->guest_R7 = 0;
1232 //ZZ vex_state->guest_R8 = 0;
1233 //ZZ vex_state->guest_R9 = 0;
1234 //ZZ vex_state->guest_R10 = 0;
1235 //ZZ vex_state->guest_R11 = 0;
1236 //ZZ vex_state->guest_R12 = 0;
1237 //ZZ vex_state->guest_R13 = 0;
1238 //ZZ vex_state->guest_R14 = 0;
1239 //ZZ vex_state->guest_R15T = 0; /* NB: implies ARM mode */
1241 vex_state->guest_CC_OP = ARM64G_CC_OP_COPY;
1242 //ZZ vex_state->guest_CC_DEP1 = 0;
1243 //ZZ vex_state->guest_CC_DEP2 = 0;
1244 //ZZ vex_state->guest_CC_NDEP = 0;
1245 //ZZ vex_state->guest_QFLAG32 = 0;
1246 //ZZ vex_state->guest_GEFLAG0 = 0;
1247 //ZZ vex_state->guest_GEFLAG1 = 0;
1248 //ZZ vex_state->guest_GEFLAG2 = 0;
1249 //ZZ vex_state->guest_GEFLAG3 = 0;
1251 //ZZ vex_state->guest_EMNOTE = EmNote_NONE;
1252 //ZZ vex_state->guest_CMSTART = 0;
1253 //ZZ vex_state->guest_CMLEN = 0;
1254 //ZZ vex_state->guest_NRADDR = 0;
1255 //ZZ vex_state->guest_IP_AT_SYSCALL = 0;
1257 //ZZ vex_state->guest_D0 = 0;
1258 //ZZ vex_state->guest_D1 = 0;
1259 //ZZ vex_state->guest_D2 = 0;
1260 //ZZ vex_state->guest_D3 = 0;
1261 //ZZ vex_state->guest_D4 = 0;
1262 //ZZ vex_state->guest_D5 = 0;
1263 //ZZ vex_state->guest_D6 = 0;
1264 //ZZ vex_state->guest_D7 = 0;
1265 //ZZ vex_state->guest_D8 = 0;
1266 //ZZ vex_state->guest_D9 = 0;
1267 //ZZ vex_state->guest_D10 = 0;
1268 //ZZ vex_state->guest_D11 = 0;
1269 //ZZ vex_state->guest_D12 = 0;
1270 //ZZ vex_state->guest_D13 = 0;
1271 //ZZ vex_state->guest_D14 = 0;
1272 //ZZ vex_state->guest_D15 = 0;
1273 //ZZ vex_state->guest_D16 = 0;
1274 //ZZ vex_state->guest_D17 = 0;
1275 //ZZ vex_state->guest_D18 = 0;
1276 //ZZ vex_state->guest_D19 = 0;
1277 //ZZ vex_state->guest_D20 = 0;
1278 //ZZ vex_state->guest_D21 = 0;
1279 //ZZ vex_state->guest_D22 = 0;
1280 //ZZ vex_state->guest_D23 = 0;
1281 //ZZ vex_state->guest_D24 = 0;
1282 //ZZ vex_state->guest_D25 = 0;
1283 //ZZ vex_state->guest_D26 = 0;
1284 //ZZ vex_state->guest_D27 = 0;
1285 //ZZ vex_state->guest_D28 = 0;
1286 //ZZ vex_state->guest_D29 = 0;
1287 //ZZ vex_state->guest_D30 = 0;
1288 //ZZ vex_state->guest_D31 = 0;
1293 //ZZ vex_state->guest_FPSCR = 0;
1295 //ZZ vex_state->guest_TPIDRURO = 0;
1298 //ZZ vex_state->guest_ITSTATE = 0;
1300 //ZZ vex_state->padding1 = 0;
1301 //ZZ vex_state->padding2 = 0;
1302 //ZZ vex_state->padding3 = 0;
1303 //ZZ vex_state->padding4 = 0;
1304 //ZZ vex_state->padding5 = 0;
