Lines Matching defs:rM
2802 x 0 0 01011 sh 0 Rm imm6 Rn Rd ADD Rd,Rn, sh(Rm,imm6)
2803 x 0 1 01011 sh 0 Rm imm6 Rn Rd ADDS Rd,Rn, sh(Rm,imm6)
2804 x 1 0 01011 sh 0 Rm imm6 Rn Rd SUB Rd,Rn, sh(Rm,imm6)
2805 x 1 1 01011 sh 0 Rm imm6 Rn Rd SUBS Rd,Rn, sh(Rm,imm6)
2812 UInt rM = INSN(20,16);
2824 IRTemp argR = getShiftedIRegOrZR(is64, sh, imm6, rM, False);
2835 nameIRegOrZR(is64, rM), nameSH(sh), imm6);
2845 x 0 0 11010 00 0 Rm 000000 Rn Rd ADC Rd,Rn,Rm
2846 x 0 1 11010 00 0 Rm 000000 Rn Rd ADCS Rd,Rn,Rm
2847 x 1 0 11010 00 0 Rm 000000 Rn Rd SBC Rd,Rn,Rm
2848 x 1 1 11010 00 0 Rm 000000 Rn Rd SBCS Rd,Rn,Rm
2855 UInt rM = INSN(20,16);
2871 assign(argR, getIRegOrZR(is64, rM));
2898 nameIRegOrZR(is64, rM));
2910 x 00 01010 sh N Rm imm6 Rn Rd AND Rd,Rn, inv?(sh(Rm,imm6))
2911 x 01 01010 sh N Rm imm6 Rn Rd ORR Rd,Rn, inv?(sh(Rm,imm6))
2912 x 10 01010 sh N Rm imm6 Rn Rd EOR Rd,Rn, inv?(sh(Rm,imm6))
2913 x 11 01010 sh N Rm imm6 Rn Rd ANDS Rd,Rn, inv?(sh(Rm,imm6))
2920 UInt rM = INSN(20,16);
2931 IRTemp argR = getShiftedIRegOrZR(is64, sh, imm6, rM, bN == 1);
2953 nameIRegOrZR(is64, rM));
2957 nameIRegOrZR(is64, rM), nameSH(sh), imm6);
2965 10011011 1 10 Rm 011111 Rn Rd UMULH Xd,Xn,Xm
2966 10011011 0 10 Rm 011111 Rn Rd SMULH Xd,Xn,Xm
2985 sf 00 11011 000 m 0 a n r MADD Rd,Rn,Rm,Ra d = a+m*n
2986 sf 00 11011 000 m 1 a n r MADD Rd,Rn,Rm,Ra d = a-m*n
3017 sf 00 1101 0100 mm cond 00 nn dd CSEL Rd,Rn,Rm
3018 sf 00 1101 0100 mm cond 01 nn dd CSINC Rd,Rn,Rm
3019 sf 10 1101 0100 mm cond 00 nn dd CSINV Rd,Rn,Rm
3020 sf 10 1101 0100 mm cond 01 nn dd CSNEG Rd,Rn,Rm
3021 In all cases, the operation is: Rd = if cond then Rn else OP(Rm)
3065 100 01011 00 1 m opt imm3 n d ADD Xd|SP, Xn|SP, Rm ext&lsld
3068 101 01011 00 1 m opt imm3 n d ADDS Xd, Xn|SP, Rm ext&lsld
3071 110 01011 00 1 m opt imm3 n d SUB Xd|SP, Xn|SP, Rm ext&lsld
3074 111 01011 00 1 m opt imm3 n d SUBS Xd, Xn|SP, Rm ext&lsld
3224 sf 1 111010010 Rm cond 00 Rn 0 nzcv CCMP Rn, Rm, #nzcv, cond
3225 sf 0 111010010 Rm cond 00 Rn 0 nzcv CCMN Rn, Rm, #nzcv, cond
3227 (CCMP) flags = if cond then flags-after-sub(Rn,Rm) else nzcv
3228 (CCMN) flags = if cond then flags-after-add(Rn,Rm) else nzcv
3380 sf 00 1101 0110 m 0010 00 n d LSLV Rd,Rn,Rm
3381 sf 00 1101 0110 m 0010 01 n d LSRV Rd,Rn,Rm
3382 sf 00 1101 0110 m 0010 10 n d ASRV Rd,Rn,Rm
3383 sf 00 1101 0110 m 0010 11 n d RORV Rd,Rn,Rm
3441 sf 00 1101 0110 m 00001 1 n d SDIV Rd,Rn,Rm
3442 sf 00 1101 0110 m 00001 0 n d UDIV Rd,Rn,Rm
4469 Rm is insn[20:16]. Rn is insn[9:5]. Rt is insn[4:0]. Log2 of
4940 11 111000011 Rm option S 10 Rn Rt LDR Xt, [Xn|SP, R<m>{ext/sh}]
4941 10 111000011 Rm option S 10 Rn Rt LDR Wt, [Xn|SP, R<m>{ext/sh}]
4942 01 111000011 Rm option S 10 Rn Rt LDRH Wt, [Xn|SP, R<m>{ext/sh}]
4943 00 111000011 Rm option S 10 Rn Rt LDRB Wt, [Xn|SP, R<m>{ext/sh}]
4945 11 111000001 Rm option S 10 Rn Rt STR Xt, [Xn|SP, R<m>{ext/sh}]
4946 10 111000001 Rm option S 10 Rn Rt STR Wt, [Xn|SP, R<m>{ext/sh}]
4947 01 111000001 Rm option S 10 Rn Rt STRH Wt, [Xn|SP, R<m>{ext/sh}]
4948 00 111000001 Rm option S 10 Rn Rt STRB Wt, [Xn|SP, R<m>{ext/sh}]
5359 00 111100 011 Rm option S 10 Rn Rt LDR Bt, [Xn|SP, R<m>{ext/sh}]
5360 01 111100 011 Rm option S 10 Rn Rt LDR Ht, [Xn|SP, R<m>{ext/sh}]
5361 10 111100 011 Rm option S 10 Rn Rt LDR St, [Xn|SP, R<m>{ext/sh}]
5362 11 111100 011 Rm option S 10 Rn Rt LDR Dt, [Xn|SP, R<m>{ext/sh}]
5363 00 111100 111 Rm option S 10 Rn Rt LDR Qt, [Xn|SP, R<m>{ext/sh}]
5365 00 111100 001 Rm option S 10 Rn Rt STR Bt, [Xn|SP, R<m>{ext/sh}]
5366 01 111100 001 Rm option S 10 Rn Rt STR Ht, [Xn|SP, R<m>{ext/sh}]
5367 10 111100 001 Rm option S 10 Rn Rt STR St, [Xn|SP, R<m>{ext/sh}]
5368 11 111100 001 Rm option S 10 Rn Rt STR Dt, [Xn|SP, R<m>{ext/sh}]
5369 00 111100 101 Rm option S 10 Rn Rt STR Qt, [Xn|SP, R<m>{ext/sh}]
5440 10 1110001 01 Rm opt S 10 Rn Rt LDRSW Xt, [Xn|SP, R<m>{ext/sh}]
5442 01 1110001 01 Rm opt S 10 Rn Rt LDRSH Xt, [Xn|SP, R<m>{ext/sh}]
5443 01 1110001 11 Rm opt S 10 Rn Rt LDRSH Wt, [Xn|SP, R<m>{ext/sh}]
5445 00 1110001 01 Rm opt S 10 Rn Rt LDRSB Xt, [Xn|SP, R<m>{ext/sh}]
5446 00 1110001 11 Rm opt S 10 Rn Rt LDRSB Wt, [Xn|SP, R<m>{ext/sh}]
6416 11 1110001 01 Rm opt S 10 Rn Rt PRFM pfrop=Rt, [Xn|SP, R<m>{ext/sh}]
9408 IRTemp rm = mk_get_IR_rounding_mode();
9410 assign(res, triop(opMUL, mkexpr(rm),
9411 binop(opCVT, mkexpr(rm), mkexpr(src)), scaleE));
9446 IRTemp rm = newTemp(Ity_I32);
9448 assign(rm, mkU32(Irrm_ZERO));
9449 assign(res, binop(opCVT, mkexpr(rm),
9450 triop(opMUL, mkexpr(rm), mkexpr(src), scaleE)));
10112 IRTemp rm = mk_get_IR_rounding_mode();
10113 putQRegLO(dd, binop(iop, mkexpr(rm), getQRegLO(nn, tyI)));
10145 IRTemp rm = mk_get_IR_rounding_mode();
10146 assign(res, binop(op, mkexpr(rm), getQRegLane(nn, 0, ty)));
10204 IRTemp rm = mk_get_IR_rounding_mode();
10208 assign(t1, triop(opMUL, mkexpr(rm), getQReg128(nn), mkexpr(dupd)));
10210 mkexpr(rm), getQReg128(dd), mkexpr(t1)));
10236 IRTemp rm = mk_get_IR_rounding_mode();
10239 assign(t1, triop(opMUL, mkexpr(rm), getQReg128(nn), mkexpr(dupd)));
10768 IRTemp rm = mk_get_IR_rounding_mode();
10770 assign(res, triop(opMUL, mkexpr(rm),
10771 binop(opCVT, mkexpr(rm), mkexpr(src)),
10814 IRTemp rm = newTemp(Ity_I32);
10816 assign(rm, mkU32(Irrm_ZERO));
10817 assign(res, binop(opCVT, mkexpr(rm),
10818 triop(opMUL, mkexpr(rm),
11597 IRTemp rm = mk_get_IR_rounding_mode();
11602 mkexpr(rm), getQReg128(nn), getQReg128(mm)));
11604 mkexpr(rm), getQReg128(dd), mkexpr(t1)));
11621 IRTemp rm = mk_get_IR_rounding_mode();
11624 assign(t1, triop(op, mkexpr(rm), getQReg128(nn), getQReg128(mm)));
11639 IRTemp rm = mk_get_IR_rounding_mode();
11643 assign(t1, triop(opSUB, mkexpr(rm), getQReg128(nn), getQReg128(mm)));
11659 IRTemp rm = mk_get_IR_rounding_mode();
11662 mkexpr(rm), getQReg128(nn), getQReg128(mm)));
11783 IRTemp rm = mk_get_IR_rounding_mode();
11786 assign(t1, triop(op, mkexpr(rm), getQReg128(nn), getQReg128(mm)));
12210 IRTemp rm = mk_get_IR_rounding_mode();
12218 binop(opCvt, mkexpr(rm), mkexpr(src[i])));
12291 /* rm plan:
12435 IRTemp rm = mk_get_IR_rounding_mode();
12440 binop(iop, mkexpr(rm), getQRegLane(nn, i, tyI)));
12536 IRTemp rm = mk_get_IR_rounding_mode();
12540 assign(t1, triop(opMUL, mkexpr(rm), getQReg128(nn), mkexpr(dupd)));
12542 mkexpr(rm), getQReg128(dd), mkexpr(t1)));
13129 rm
13131 rm (17:15) encodings:
13142 UInt rm = opcode & BITS6(0,0,0,1,1,1);
13146 switch (rm) {
13315 IRExpr* rm = mkexpr(mk_get_IR_rounding_mode());
13316 IRExpr* eNxM = triop(opMUL, rm, eN, eM);
13318 case 0: assign(res, triop(opADD, rm, eA, eNxM)); break;
13319 case 1: assign(res, triop(opSUB, rm, eA, eNxM)); break;
13320 case 2: assign(res, unop(opNEG, triop(opADD, rm, eA, eNxM))); break;
13321 case 3: assign(res, unop(opNEG, triop(opSUB, rm, eA, eNxM))); break;
13392 UInt rm = INSN(20,19); // rmode
13398 if (ty <= X01 && rm == X11
13400 /* -------- (ix) sf ty rm opc -------- */
13440 /* ------ sf,ty,rm,opc ------ */
13443 /* (ix) sf S 28 ty rm opc 15 9 4
13458 if (ty <= X01 && rm == X00
13513 UInt rm = INSN(20,19); // rmode
13535 || ((op == BITS3(1,0,0) || op == BITS3(1,0,1)) && rm == BITS2(0,0))
13545 switch (rm) {
13554 switch (rm) {
13637 /* (ix) sf S 28 ty rm op 15 9 4
13651 if (ty <= X01 && rm == X00 && (op == BITS3(0,1,0) || op == BITS3(0,1,1))) {
13674 /* case sf S ty rm op 15 9 4
13686 if (ty == BITS2(0,0) && rm == BITS2(0,0) && op == BITS3(1,1,1))
13689 if (ty == BITS2(0,0) && rm == BITS2(0,0) && op == BITS3(1,1,0))
13693 if (ty == BITS2(0,1) && rm == BITS2(0,0) && op == BITS3(1,1,1))
13696 if (ty == BITS2(0,1) && rm == BITS2(0,0) && op == BITS3(1,1,0))
13699 if (ty == BITS2(1,0) && rm == BITS2(0,1) && op == BITS3(1,1,1))
13702 if (ty == BITS2(1,0) && rm == BITS2(0,1) && op == BITS3(1,1,0))
