Lines Matching full:vex_state
947 /*OUT*/VexGuestARMState* vex_state )
955 vex_state->guest_CC_OP = ARMG_CC_OP_COPY;
956 vex_state
957 vex_state->guest_CC_DEP2 = 0;
958 vex_state->guest_CC_NDEP = 0;
963 UInt LibVEX_GuestARM_get_cpsr ( /*IN*/const VexGuestARMState* vex_state )
968 vex_state->guest_CC_OP,
969 vex_state->guest_CC_DEP1,
970 vex_state->guest_CC_DEP2,
971 vex_state->guest_CC_NDEP
975 if (vex_state->guest_QFLAG32 > 0)
978 if (vex_state->guest_GEFLAG0 > 0)
980 if (vex_state->guest_GEFLAG1 > 0)
982 if (vex_state->guest_GEFLAG2 > 0)
984 if (vex_state->guest_GEFLAG3 > 0)
990 if (vex_state->guest_R15T & 1)
1001 void LibVEX_GuestARM_initialise ( /*OUT*/VexGuestARMState* vex_state )
1003 vex_state->host_EvC_FAILADDR = 0;
1004 vex_state->host_EvC_COUNTER = 0;
1006 vex_state->guest_R0 = 0;
1007 vex_state->guest_R1 = 0;
1008 vex_state->guest_R2 = 0;
1009 vex_state->guest_R3 = 0;
1010 vex_state->guest_R4 = 0;
1011 vex_state->guest_R5 = 0;
1012 vex_state->guest_R6 = 0;
1013 vex_state->guest_R7 = 0;
1014 vex_state->guest_R8 = 0;
1015 vex_state->guest_R9 = 0;
1016 vex_state->guest_R10 = 0;
1017 vex_state->guest_R11 = 0;
1018 vex_state->guest_R12 = 0;
1019 vex_state->guest_R13 = 0;
1020 vex_state->guest_R14 = 0;
1021 vex_state->guest_R15T = 0; /* NB: implies ARM mode */
1023 vex_state->guest_CC_OP = ARMG_CC_OP_COPY;
1024 vex_state->guest_CC_DEP1 = 0;
1025 vex_state->guest_CC_DEP2 = 0;
1026 vex_state->guest_CC_NDEP = 0;
1027 vex_state->guest_QFLAG32 = 0;
1028 vex_state->guest_GEFLAG0 = 0;
1029 vex_state->guest_GEFLAG1 = 0;
1030 vex_state->guest_GEFLAG2 = 0;
1031 vex_state->guest_GEFLAG3 = 0;
1033 vex_state->guest_EMNOTE = EmNote_NONE;
1034 vex_state->guest_CMSTART = 0;
1035 vex_state->guest_CMLEN = 0;
1036 vex_state->guest_NRADDR = 0;
1037 vex_state->guest_IP_AT_SYSCALL = 0;
1039 vex_state->guest_D0 = 0;
1040 vex_state->guest_D1 = 0;
1041 vex_state->guest_D2 = 0;
1042 vex_state->guest_D3 = 0;
1043 vex_state->guest_D4 = 0;
1044 vex_state->guest_D5 = 0;
1045 vex_state->guest_D6 = 0;
1046 vex_state->guest_D7 = 0;
1047 vex_state->guest_D8 = 0;
1048 vex_state->guest_D9 = 0;
1049 vex_state->guest_D10 = 0;
1050 vex_state->guest_D11 = 0;
1051 vex_state->guest_D12 = 0;
1052 vex_state->guest_D13 = 0;
1053 vex_state->guest_D14 = 0;
1054 vex_state->guest_D15 = 0;
1055 vex_state->guest_D16 = 0;
1056 vex_state->guest_D17 = 0;
1057 vex_state->guest_D18 = 0;
1058 vex_state->guest_D19 = 0;
1059 vex_state->guest_D20 = 0;
1060 vex_state->guest_D21 = 0;
1061 vex_state->guest_D22 = 0;
1062 vex_state->guest_D23 = 0;
1063 vex_state->guest_D24 = 0;
1064 vex_state->guest_D25 = 0;
1065 vex_state->guest_D26 = 0;
1066 vex_state->guest_D27 = 0;
1067 vex_state->guest_D28 = 0;
1068 vex_state->guest_D29 = 0;
1069 vex_state->guest_D30 = 0;
1070 vex_state->guest_D31 = 0;
1075 vex_state->guest_FPSCR = 0;
1077 vex_state->guest_TPIDRURO = 0;
1080 vex_state->guest_ITSTATE = 0;
1082 vex_state->padding1 = 0;
