Lines Matching defs:rM
1734 UInt rM /* only for debug printing */
1742 DIS(buf, "r%u", rM);
1754 DIS(buf, "r%u, LSL #%u", rM, shift_amt);
1764 UInt rM, UInt rS /* only for debug printing */
1769 // res = amt < 32 ? Rm << amt : 0
1771 // amt in 1..32 ? Rm[32-amt] : 0
1778 Rm[(32-amt) & 31]),
1811 // (Rm << (Rs & 31)) & (((Rs & 255) - 32) >>s 31)
1828 DIS(buf, "r%u, LSL r%u", rM, rS);
1837 UInt rM /* only for debug printing */
1843 // newC = Rm[31]
1851 DIS(buf, "r%u, LSR #0(a.k.a. 32)", rM);
1854 // res = Rm >>u shift_amt
1855 // newC = Rm[shift_amt - 1]
1866 DIS(buf, "r%u, LSR #%u", rM, shift_amt);
1876 UInt rM, UInt rS /* only for debug printing */
1881 // res = amt < 32 ? Rm >>u amt : 0
1883 // amt in 1..32 ? Rm[amt-1] : 0
1890 Rm[(amt-1) & 31]),
1921 // (Rm >>u (Rs & 31)) & (((Rs & 255) - 32) >>s 31)
1938 DIS(buf, "r%u, LSR r%u", rM, rS);
1947 UInt rM /* only for debug printing */
1952 // res = Rm >>s 31
1953 // newC = Rm[31]
1961 DIS(buf, "r%u, ASR #0(a.k.a. 32)", rM);
1964 // res = Rm >>s shift_amt
1965 // newC = Rm[shift_amt - 1]
1976 DIS(buf, "r%u, ASR #%u", rM, shift_amt);
1986 UInt rM, UInt rS /* only for debug printing */
1991 // res = amt < 32 ? Rm >>s amt : Rm >>s 31
1993 // amt in 1..32 ? Rm[amt-1] : Rm[31]
1999 Rm[31],
2000 Rm[(amt-1) & 31])
2037 // (Rm >>s (amt <u 32 ? amt : 31))
2049 DIS(buf, "r%u, ASR r%u", rM, rS);
2058 UInt rM, UInt rS /* only for debug printing */
2063 // shop = Rm `ror` (amt & 31)
2064 // shco = amt == 0 ? oldC : Rm[(amt-1) & 31]
2114 DIS(buf, "r%u, ROR r#%u", rM, rS);
2140 UInt rM /* only for debug printing */
2150 buf, res, newC, rMt, shift_amt, rM
2156 buf, res, newC, rMt, shift_amt, rM
2162 buf, res, newC, rMt, shift_amt, rM
2171 // res = (oldC << 31) | (Rm >>u 1)
2172 // newC = Rm[0]
2182 DIS(buf, "r%u, RRX", rM);
2185 // res = Rm `ror` shift_amt
2186 // newC = Rm[shift_amt - 1]
2200 DIS(buf, "r%u, ROR #%u", rM, shift_amt);
2233 UInt rM, /* only for debug printing */
2241 buf, res, newC, rMt, rSt, rM, rS
2247 buf, res, newC, rMt, rSt, rM, rS
2253 buf, res, newC, rMt, rSt, rM, rS
2259 buf, res, newC, rMt, rSt, rM, rS
2324 /* Rm (3:0) shifted (6:5) by immediate (11:7) */
2326 UInt rM = (insn_11_0 >> 0) & 0xF;
2330 assign(rMt, getIRegA(rM));
2335 buf, shop, shco, rMt, how, shift_amt, rM
2342 /* Rm (3:0) shifted (6:5) by Rs (11:8) */
2343 UInt rM = (insn_11_0 >> 0) & 0xF;
2353 assign(rMt, getIRegA(rM));
2357 buf, shop, shco, rMt, how, rSt, rM, rS
2388 IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM,
2394 vassert(rM < 16);
2402 index = binop(Iop_Shl32, getIRegA(rM), mkU8(imm5));
2403 DIS(buf, "[r%u, %c r%u LSL #%u]", rN, opChar, rM, imm5);
2410 index = binop(Iop_Shr32, getIRegA(rM), mkU8(imm5));
2413 rN, opChar, rM, imm5 == 0 ? 32 : imm5);
2419 index = binop(Iop_Sar32, getIRegA(rM), mkU8(31));
2422 index = binop(Iop_Sar32, getIRegA(rM), mkU8(imm5));
2425 rN, opChar, rM, imm5 == 0 ? 32 : imm5);
2431 assign(rmT, getIRegA(rM));
2436 DIS(buf, "[r%u, %cr%u, RRX]", rN, opChar, rM);
2439 assign(rmT, getIRegA(rM));
2444 DIS(buf, "[r%u, %cr%u, ROR #%u]", rN, opChar, rM, imm5);
2475 IRExpr* mk_EA_reg_plusminus_reg ( UInt rN, UInt bU, UInt rM,
2480 vassert(rM < 16);
2482 IRExpr* index = getIRegA(rM);
2483 DIS(buf, "[r%u, %c r%u]", rN, opChar, rM);
8335 UInt rM = INSN(3,0);
8355 assign(initialRm, isT ? getIRegT(rM) : getIRegA(rM));
8397 if (rM != 13 && rM != 15) {
8398 DIP(", r%u\n", rM);
8400 DIP("%s\n", (rM != 15) ? "!" : "");
8494 if (rM != 13 && rM != 15) {
8495 DIP(", r%u\n", rM);
8497 DIP("%s\n", (rM != 15) ? "!" : "");
8501 if (rM != 15) {
8502 if (rM == 13) {
8771 if (rM != 15) {
8773 if (rM == 13) {
8801 if (rM != 13 && rM != 15) {
8802 DIP(", r%u\n", rM);
8804 DIP("%s\n", (rM != 15) ? "!" : "");
9002 /* ------------ smulwb<y><c> <Rd>,<Rn>,<Rm> ------------- */
9003 /* ------------ smulwt<y><c> <Rd>,<Rn>,<Rm> ------------- */
9063 /* ------------ pkhbt<c> Rd, Rn, Rm {,LSL #imm} ------------- */
9064 /* ------------ pkhtb<c> Rd, Rn, Rm {,ASR #imm} ------------- */
9365 /* -------------- uadd16<c> <Rd>,<Rn>,<Rm> -------------- */
9414 /* -------------- sadd16<c> <Rd>,<Rn>,<Rm> -------------- */
9464 /* ---------------- usub16<c> <Rd>,<Rn>,<Rm> ---------------- */
9514 /* -------------- ssub16<c> <Rd>,<Rn>,<Rm> -------------- */
9564 /* ----------------- uadd8<c> <Rd>,<Rn>,<Rm> ---------------- */
9613 /* ------------------- sadd8<c> <Rd>,<Rn>,<Rm> ------------------ */
9663 /* ------------------- usub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9713 /* ------------------- ssub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9763 /* ------------------ qadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9808 /* ------------------ qsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
9853 /* ------------------ uqadd8<c> <Rd>,<Rn>,<Rm> ------------------ */
9898 /* ------------------ uqsub8<c> <Rd>,<Rn>,<Rm> ------------------ */
9943 /* ----------------- uhadd8<c> <Rd>,<Rn>,<Rm> ------------------- */
9988 /* ----------------- uhadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
10033 Rm> ------------------- */
10078 /* ------------------ qadd16<c> <Rd>,<Rn>,<Rm> ------------------ */
10123 /* ------------------ qsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
10168 /* ------------------- qsax<c> <Rd>,<Rn>,<Rm> ------------------- */
10239 /* ------------------- qasx<c> <Rd>,<Rn>,<Rm> ------------------- */
10307 /* ------------------- sasx<c> <Rd>,<Rn>,<Rm> ------------------- */
10381 /* --------------- smuad, smuadx<c><Rd>,<Rn>,<Rm> --------------- */
10382 /* --------------- smsad, smsadx<c><Rd>,<Rn>,<Rm> --------------- */
10460 /* --------------- smlad{X}<c> <Rd>,<Rn>,<Rm>,<Ra> -------------- */
10461 /* --------------- smlsd{X}<c> <Rd>,<Rn>,<Rm>,<Ra> -------------- */
10551 /* ----- smlabb, smlabt, smlatb, smlatt <Rd>,<Rn>,<Rm>,<Ra> ----- */
10621 /* ----- smlalbb, smlalbt, smlaltb, smlaltt <Rd>,<Rn>,<Rm>,<Ra> ----- */
10696 /* ----- smlawb, smlawt <Rd>,<Rn>,<Rm>,<Ra> ----- */
10767 /* ------------------- sel<c> <Rd>,<Rn>,<Rm> -------------------- */
10855 /* ----------------- uxtab16<c> Rd,Rn,Rm{,rot} ------------------ */
10918 /* --------------- usad8 Rd,Rn,Rm ---------------- */
10919 /* --------------- usada8 Rd,Rn,Rm,Ra ---------------- */
10921 UInt rD = 99, rN = 99, rM = 99, rA = 99;
10929 rM = INSNT1(3,0);
10930 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && rA != 13)
10938 rM = INSNA(11,8);
10940 if (rD != 15 && rN != 15 && rM != 15 /* but rA can be 15 */)
10948 IRExpr* rMe = isT ? getIRegT(rM) : getIRegA(rM);
10961 nCC(conq), rD, rN, rM );
10964 nCC(conq), rD, rN, rM, rA );
10971 /* ------------------ qadd<c> <Rd>,<Rn>,<Rm> ------------------- */
11022 /* ------------------ qdadd<c> <Rd>,<Rm>,<Rn> ------------------- */
11081 /* ------------------ qsub<c> <Rd>,<Rn>,<Rm> ------------------- */
11132 /* ------------------ qdsub<c> <Rd>,<Rm>,<Rn> ------------------- */
11191 /* ------------------ uqsub16<c> <Rd>,<Rn>,<Rm> ------------------ */
11236 /* ----------------- shadd16<c> <Rd>,<Rn>,<Rm> ------------------- */
11281 /* ----------------- uhsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
11326 /* ----------------- uhsub16<c> <Rd>,<Rn>,<Rm> ------------------- */
11371 /* ------------------ uqadd16<c> <Rd>,<Rn>,<Rm> ------------------ */
11416 /* ------------------- uqsax<c> <Rd>,<Rn>,<Rm> ------------------- */
11485 /* ------------------- uqasx<c> <Rd>,<Rn>,<Rm> ------------------- */
11553 /* ------------------- usax<c> <Rd>,<Rn>,<Rm> ------------------- */
11631 /* ------------------- uasx<c> <Rd>,<Rn>,<Rm> ------------------- */
11707 /* ------------------- ssax<c> <Rd>,<Rn>,<Rm> ------------------- */
11781 /* ----------------- shsub8<c> <Rd>,<Rn>,<Rm> ------------------- */
11826 /* ----------------- sxtab16<c> Rd,Rn,Rm{,rot} ------------------ */
11901 /* ----------------- shasx<c> <Rd>,<Rn>,<Rm> ------------------- */
11998 /* ----------------- uhasx<c> <Rd>,<Rn>,<Rm> ------------------- */
12095 /* ----------------- shsax<c> <Rd>,<Rn>,<Rm> ------------------- */
12192 /* ----------------- uhsax<c> <Rd>,<Rn>,<Rm> ------------------- */
12289 /* ----------------- shsub16<c> <Rd>,<Rn>,<Rm> ------------------- */
12334 /* ----------------- smmls{r}<c> <Rd>,<Rn>,<Rm>,<Ra> ------------------- */
12336 UInt rD = 99, rN = 99, rM = 99, rA = 99;
12347 rM = INSNT1(3,0);
12350 && !isBadRegT(rN) && !isBadRegT(rM) && !isBadRegT(rA))
12360 rM = INSNA(11,8);
12362 if (rD != 15 && rM != 15 && rN != 15)
12372 assign( irt_rM, isT ? getIRegT(rM) : getIRegA(rM) );
12385 round ? "r" : "", nCC(conq), rD, rN, rM, rA);
12391 /* -------------- smlald{x}<c> <RdLo>,<RdHi>,<Rn>,<Rm> ---------------- */
12393 UInt rN = 99, rDlo = 99, rDhi = 99, rM = 99;
12403 rM = INSNT1(3,0);
12406 && !isBadRegT(rM) && rDhi != rDlo)
12415 rM = INSNA(11,8);
12418 && rN != 15 && rM != 15 && rDlo != rDhi)
12434 assign( irt_rM, isT ? getIRegT(rM) : getIRegA(rM));
12474 m_swap ? 'x' : ' ', nCC(conq), rDlo, rDhi, rN, rM);
12480 /* -------------- smlsld{x}<c> <RdLo>,<RdHi>,<Rn>,<Rm> ---------------- */
12482 UInt rN = 99, rDlo = 99, rDhi = 99, rM = 99;
12492 rM = INSNT1(3,0);
12495 !isBadRegT(rM) && rDhi != rDlo)
12504 rM = INSNA(11,8);
12507 rN != 15 && rM != 15 && rDlo != rDhi)
12522 assign( irt_rM, isT ? getIRegT(rM) : getIRegA(rM) );
12562 m_swap ? 'x' : ' ', nCC(conq), rDlo, rDhi, rN, rM);
13194 // VMOV sD, sD+1, rN, rM
13198 UInt rM = INSN(19,16);
13199 if (rM == 15 || rN == 15 || (isT && (rM == 13 || rN == 13))
13207 unop(Iop_ReinterpI32asF32, isT ? getIRegT(rM) : getIRegA(rM)),
13210 nCC(conq), sD, sD + 1, rN, rM);
13215 // VMOV rN, rM, sD, sD+1
13219 UInt rM = INSN(19,16);
13220 if (rM == 15 || rN == 15 || (isT && (rM == 13 || rN == 13))
13221 || sD == 31 || rN == rM) {
13228 putIRegT(rM, res1, condT);
13231 putIRegA(rM, res1, condT, Ijk_Boring);
13234 nCC(conq), rN, rM, sD, sD + 1);
13469 IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
13472 putDReg(dD, triop(Iop_AddF64, rm,
13474 triop(Iop_MulF64, rm, getDReg(dN),
13480 putDReg(dD, triop(Iop_AddF64, rm,
13483 triop(Iop_MulF64, rm, getDReg(dN),
13489 putDReg(dD, triop(Iop_AddF64, rm,
13491 triop(Iop_MulF64, rm, getDReg(dN),
13497 putDReg(dD, triop(Iop_AddF64, rm,
13500 triop(Iop_MulF64, rm, getDReg(dN),
13506 putDReg(dD, triop(Iop_MulF64, rm, getDReg(dN), getDReg(dM)),
13512 triop(Iop_MulF64, rm, getDReg(dN),
13518 putDReg(dD, triop(Iop_AddF64, rm, getDReg(dN), getDReg(dM)),
13523 putDReg(dD, triop(Iop_SubF64, rm, getDReg(dN), getDReg(dM)),
13528 putDReg(dD, triop(Iop_DivF64, rm, getDReg(dN), getDReg(dM)),
13535 putDReg(dD, triop(Iop_AddF64, rm,
13537 triop(Iop_MulF64, rm,
13546 putDReg(dD, triop(Iop_AddF64, rm,
13548 triop(Iop_MulF64, rm,
13557 putDReg(dD, triop(Iop_AddF64, rm,
13559 triop(Iop_MulF64, rm, getDReg(dN),
13567 putDReg(dD, triop(Iop_AddF64, rm,
13569 triop(Iop_MulF64, rm,
13681 IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
13682 putDReg(dD, binop(Iop_SqrtF64, rm, getDReg(dM)), condT);
13977 IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
13980 putFReg(fD, triop(Iop_AddF32, rm,
13982 triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
13987 putFReg(fD, triop(Iop_AddF32, rm,
13990 triop(Iop_MulF32, rm, getFReg(fN),
13996 putFReg(fD, triop(Iop_AddF32, rm,
13998 triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
14003 putFReg(fD, triop(Iop_AddF32, rm,
14006 triop(Iop_MulF32, rm,
14013 putFReg(fD, triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM)),
14019 triop(Iop_MulF32, rm, getFReg(fN),
14025 putFReg(fD, triop(Iop_AddF32, rm, getFReg(fN), getFReg(fM)),
14030 putFReg(fD, triop(Iop_SubF32, rm, getFReg(fN), getFReg(fM)),
14035 putFReg(fD, triop(Iop_DivF32, rm, getFReg(fN), getFReg(fM)),
14042 putFReg(fD, triop(Iop_AddF32, rm,
14044 triop(Iop_MulF32, rm,
14053 putFReg(fD, triop(Iop_AddF32, rm,
14055 triop(Iop_MulF32, rm,
14064 putFReg(fD, triop(Iop_AddF32, rm,
14066 triop(Iop_MulF32, rm, getFReg(fN),
14074 putFReg(fD, triop(Iop_AddF32, rm,
14076 triop(Iop_MulF32, rm,
14195 IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
14196 putFReg(fD, binop(Iop_SqrtF32, rm, getFReg(fM)), condT);
14342 IRExpr* rm = mkU32(Irrm_NEAREST);
14358 rm, as_F64,
14359 triop(Iop_AddF64, rm, mkexpr(scale),
14377 rm, as_F64,
14378 triop(Iop_AddF64, rm, mkexpr(scale),
14392 rm, mkexpr(srcF64),
14393 triop(Iop_AddF64, rm, mkexpr(scale),
14414 rm, unop(Iop_F32toF64, mkexpr(srcF32)),
14415 triop(Iop_AddF64, rm, mkexpr(scale),
14483 UInt rM = INSN(3,0);
14488 if (rM != 15 && (rN != 15 || bR)) {
14489 IRExpr* eaE = mk_EA_reg_plusminus_shifted_reg(rN, bU, rM,
15065 A5-22 1 | 32 cond 0111 UBOL Rn Rd imm5 sh2 0 Rm
15067 A5-26 2 | 32 cond 0111 UB1L Rn Rd imm5 sh2 0 Rm
15069 A5-32 3 | 32 cond 0110 UB0L Rn Rd imm5 sh2 0 Rm
15077 32 Rn +/- Rm sh2 imm5
15110 UInt rM = (insn >> 0) & 0xF; /* 3:0 */
15125 if (rM == 15) goto after_load_store_ubyte_or_word;
15132 if (rM == 15) goto after_load_store_ubyte_or_word;
15134 if (rN == rM) goto after_load_store_ubyte_or_word;
15149 eaE = mk_EA_reg_plusminus_shifted_reg( rN, bU, rM, sh2, imm5,
15292 A5-38 1 | 32 cond 0001 U00L Rn Rd 0000 1SH1 Rm
15294 A5-42 2 | 32 cond 0001 U01L Rn Rd 0000 1SH1 Rm
15296 A5-46 3 | 32 cond 0000 U00L Rn Rd 0000 1SH1 Rm
15304 32 Rn +/- Rm
15338 UInt rM = (insn >> 0) & 0xF; /* 3:0 */
15353 /* Require 11:8 == 0 for Rn +/- Rm cases */
15364 if (rM == 15) goto after_load_store_sbyte_or_hword;
15371 if (rM == 15) goto after_load_store_sbyte_or_hword;
15373 if (rN == rM) goto after_load_store_sbyte_or_hword;
15400 eaE = mk_EA_reg_plusminus_reg( rN, bU, rM, dis_buf );
15652 UInt rM = INSN(3,0);
15653 // we don't decode the case (link && rM == 15), as that's
15655 if (!(link && rM == 15)) {
15659 // rM contains an interworking address exactly as we require
15662 assign( dst, getIRegA(rM) );
15669 : (rM == 14 ? Ijk_Ret : Ijk_Boring);
15672 DIP("b%sx r%u\n", link ? "l" : "", rM);
15674 DIP("b%sx%s r%u\n", link ? "l" : "", nCC(INSN_COND), rM);
15678 /* else: (link && rM == 15): just fall through */
15692 UInt rM = INSN(3,0);
15695 assign(arg, getIRegA(rM));
15702 DIP("clz%s r%u, r%u\n", nCC(INSN_COND), rD, rM);
15714 UInt rM = INSN(3,0);
15715 if (rD == 15 || rM == 15 || rS == 15) {
15723 assign( argL, getIRegA(rM));
15742 bitS ? 's' : ' ', nCC(INSN_COND), rD, rM, rS);
15754 UInt rM = INSN(11,8);
15756 if (rD == 15 || rM == 15 || rN == 15) {
15763 assign(argR, getIRegA(rM));
15766 DIP("sdiv r%u, r%u, r%u\n", rD, rN, rM);
15776 UInt rM = INSN(11,8);
15778 if (rD == 15 || rM == 15 || rN == 15) {
15785 assign(argR, getIRegA(rM));
15788 DIP("udiv r%u, r%u, r%u\n", rD, rN, rM);
15801 UInt rM = INSN(3,0);
15807 if (rD == 15 || rM == 15 || rS == 15 || rN == 15) {
15816 assign( argL, getIRegA(rM));
15840 nCC(INSN_COND), rD, rM, rS, rN);
15853 UInt rM = INSN(3,0);
15855 if (rDhi == 15 || rDlo == 15 || rM == 15 || rS == 15 || rDhi == rDlo) {
15866 assign( argL, getIRegA(rM));
15889 nCC(INSN_COND), rDlo, rDhi, rM, rS);
15902 UInt rM = INSN(3,0);
15904 if (rDhi == 15 || rDlo == 15 || rM == 15 || rS == 15 || rDhi == rDlo) {
15916 assign( argL, getIRegA(rM));
15942 rDlo, rDhi, rM, rS);
15952 UInt rM = INSN(11,8);
15954 if (rDlo == 15 || rDhi == 15 || rN == 15 || rM == 15 || rDhi == rDlo) {
15965 assign( argM, getIRegA(rM) );
15980 nCC(INSN_COND), rDlo, rDhi, rN, rM);
16064 UInt rM = INSN(3,0);
16071 if (rD == 15 || rN == 15 || rM == 15 || rN == rM || rN == rD) {
16081 assign(tNew, getIRegA(rM));
16104 isB ? "b" : "", nCC(INSN_COND), rD, rM, rN);
16272 UInt rM = INSN(3,0);
16278 assign(srcT, getIRegA(rM));
16325 DIP("%s%s r%u, r%u, ROR #%d\n", nm, nCC(INSN_COND), rD, rM, rot);
16417 A5-38 1 | 32 cond 0001 U000 Rn Rd 0000 11S1 Rm
16419 A5-42 2 | 32 cond 0001 U010 Rn Rd 0000 11S1 Rm
16421 A5-46 3 | 32 cond 0000 U000 Rn Rd 0000 11S1 Rm
16429 32 Rn +/- Rm
16463 UInt rM = (insn >> 0) & 0xF; /* 3:0 */
16472 /* Require 11:8 == 0 for Rn +/- Rm cases */
16483 if (rM == 15) goto after_load_store_doubleword;
16491 if (rM == 15) goto after_load_store_doubleword;
16493 if (rN == rM) goto after_load_store_doubleword;
16520 eaE = mk_EA_reg_plusminus_reg( rN, bU, rM, dis_buf );
16623 UInt rM = INSN(3,0);
16626 if (rN == 15/*it's {S,U}XTB*/ || rD == 15 || rM == 15) {
16632 assign(srcR, getIRegA(rM));
16641 isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
16653 UInt rM = INSN(3,0);
16656 if (rN == 15/*it's {S,U}XTH*/ || rD == 15 || rM == 15) {
16662 assign(srcR, getIRegA(rM));
16672 isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
16682 UInt rM = INSN(3,0);
16684 if (rM != 15 && rD != 15) {
16686 assign(rMt, getIRegA(rM));
16690 nCC(INSN_COND), rD, rM);
16697 UInt rM = INSN(3,0);
16699 if (rM != 15 && rD != 15) {
16704 assign(irt_rM, getIRegA(rM));
16721 DIP("revsh%s r%u, r%u\n", nCC(INSN_COND), rD, rM);
16729 UInt rM = INSN(3,0);
16730 if (rD != 15 && rM != 15) {
16732 assign(arg, getIRegA(rM));
16735 DIP("rbit r%u, r%u\n", rD, rM);
16746 UInt rM = INSN(11,8);
16748 if (rD != 15 && rM != 15 && rN != 15) {
16752 binop(Iop_MullS32, getIRegA(rN), getIRegA(rM)),
16756 nCC(INSN_COND), bitR ? "r" : "", rD, rN, rM);
16768 UInt rM = INSN(11,8);
16770 if (rD != 15 && rM != 15 && rN != 15) {
16776 binop(Iop_MullS32, getIRegA(rN), getIRegA(rM))),
16780 nCC(INSN_COND), bitR ? "r" : "", rD, rN, rM, rA);
16812 ldrt<c> Rt, [Rn], +/-Rm{, shift}
16818 UInt rM = INSN(3,0);
16823 if (rT == 15 || rN == 15 || rN == rT || rM == 15
16824 /* || (ArchVersion() < 6 && rM == rN) */)
16832 IRExpr* erN = mk_EA_reg_plusminus_shifted_reg(rN, bU, rM,
16867 ldrbt<c> Rt, [Rn], +/-Rm{, shift}
16873 UInt rM = INSN(3,0);
16878 if (rT == 15 || rN == 15 || rN == rT || rM == 15
16879 /* || (ArchVersion() < 6 && rM == rN) */)
16887 IRExpr* erN = mk_EA_reg_plusminus_shifted_reg(rN, bU, rM,
16926 ldrht<c> Rt, [Rn], +/-Rm
16932 UInt rM = INSN(3,0);
16935 if (rT == 15 || rN == 15 || rN == rT || rM == 15)
16943 getIRegA(rN), getIRegA(rM));
16946 nCC(INSN_COND), rT, rN, bU ? '+' : '-', rM);
16982 ldrsht<c> Rt, [Rn], +/-Rm
16988 UInt rM = INSN(3,0);
16991 if (rN == 15 || rT == 15 || rN == rT || rM == 15)
16999 getIRegA(rN), getIRegA(rM));
17002 nCC(INSN_COND), rT, rN, bU ? '+' : '-', rM);
17038 ldrsbt<c> Rt, [Rn], +/-Rm
17045 UInt rM = INSN(3,0);
17047 if (rT == 15 || rN == 15 || rN == rT || rM == 15)
17055 getIRegA(rN), getIRegA(rM));
17058 nCC(INSN_COND), rT, rN, bU ? '+' : '-', rM);
17089 strbt<c> Rt, [Rn], +/-Rm{, shift}
17097 UInt rM = INSN(3,0);
17100 if (rT == 15 || rN == 15 || rN == rT || rM == 15) valid = False;
17106 IRExpr* erN = mk_EA_reg_plusminus_shifted_reg(rN, bU, rM,
17143 strht<c> Rt, [Rn], +/-Rm
17149 UInt rM = INSN(3,0);
17152 if (rT == 15 || rN == 15 || rN == rT || rM == 15) valid = False;
17158 getIRegA(rN), getIRegA(rM));
17161 nCC(INSN_COND), rT, rN, bU ? '+' : '-', rM);
17191 strt<c> Rt, [Rn], +/-Rm{, shift}
17197 UInt rM = INSN(3,0);
17202 if (rN == 15 || rN == rT || rM == 15) valid = False;
17204 if ArchVersion() < 6 && rM == rN then UNPREDICTABLE */
17208 IRExpr* erN = mk_EA_reg_plusminus_shifted_reg(rN, bU, rM,
17931 /* ---------------- CMP Rn, Rm ---------------- */
17934 UInt rM = INSN0(5,3);
17938 assign( argR, getIRegT(rM) );
17942 DIP("%s r%u, r%u\n", isCMN ? "cmn" : "cmp", rN, rM);
17947 /* ---------------- TST Rn, Rm ---------------- */
17949 UInt rM = INSN0(5,3);
17955 assign( res, binop(Iop_And32, getIRegT(rN), getIRegT(rM)) );
17958 DIP("tst r%u, r%u\n", rN, rM);
17963 /* ---------------- NEGS Rd, Rm ---------------- */
17964 /* Rd = -Rm */
17965 UInt rM = INSN0(5,3);
17969 assign(arg, getIRegT(rM));
17974 DIP("negs r%u, r%u\n", rD, rM);
17979 /* ---------------- MVNS Rd, Rm ---------------- */
17980 /* Rd = ~Rm */
17981 UInt rM = INSN0(5,3);
17988 assign(res, unop(Iop_Not32, getIRegT(rM)));
17993 DIP("mvns r%u, r%u\n", rD, rM);
17998 /* ---------------- ORRS Rd, Rm ---------------- */
18001 /* ---------------- ANDS Rd, Rm ---------------- */
18004 /* ---------------- EORS Rd, Rm ---------------- */
18007 /* ---------------- MULS Rd, Rm ---------------- */
18010 /* Rd = Rd `op` Rm */
18011 UInt rM = INSN0(5,3);
18018 assign( res, binop(anOp, getIRegT(rD), getIRegT(rM) ));
18024 DIP("%s r%u, r%u\n", anOpNm, rD, rM);
18029 /* ---------------- BICS Rd, Rm ---------------- */
18030 /* Rd = Rd & ~Rm */
18031 UInt rM = INSN0(5,3);
18039 unop(Iop_Not32, getIRegT(rM) )));
18045 DIP("bics r%u, r%u\n", rD, rM);
18050 /* ---------------- ADCS Rd, Rm ---------------- */
18051 /* Rd = Rd + Rm + oldC */
18052 UInt rM = INSN0(5,3);
18059 assign(argR, getIRegT(rM));
18068 DIP("adcs r%u, r%u\n", rD, rM);
18073 /* ---------------- SBCS Rd, Rm ---------------- */
18074 /* Rd = Rd - Rm - (oldC ^ 1) */
18075 UInt rM = INSN0(5,3);
18082 assign(argR, getIRegT(rM));
18091 DIP("sbcs r%u, r%u\n", rD, rM);
18096 /* ---------------- UXTB Rd, Rm ---------------- */
18097 /* Rd = 8Uto32(Rm) */
18098 UInt rM = INSN0(5,3);
18100 putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFF)),
18102 DIP("uxtb r%u, r%u\n", rD, rM);
18107 /* ---------------- SXTB Rd, Rm ---------------- */
18108 /* Rd = 8Sto32(Rm) */
18109 UInt rM = INSN0(5,3);
18112 binop(Iop_Shl32, getIRegT(rM), mkU8(24)),
18115 DIP("sxtb r%u, r%u\n", rD, rM);
18120 /* ---------------- UXTH Rd, Rm ---------------- */
18121 /* Rd = 16Uto32(Rm) */
18122 UInt rM = INSN0(5,3);
18124 putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFFFF)),
18126 DIP("uxth r%u, r%u\n", rD, rM);
18131 /* ---------------- SXTH Rd, Rm ---------------- */
18132 /* Rd = 16Sto32(Rm) */
18133 UInt rM = INSN0(5,3);
18136 binop(Iop_Shl32, getIRegT(rM), mkU8(16)),
18139 DIP("sxth r%u, r%u\n", rD, rM);
18202 /* ---------------- REV Rd, Rm ---------------- */
18203 /* ---------------- REV16 Rd, Rm ---------------- */
18204 UInt rM = INSN0(5,3);
18208 assign(arg, getIRegT(rM));
18211 DIP("rev%s r%u, r%u\n", isREV ? "" : "16", rD, rM);
18217 UInt rM = INSN0(5,3);
18223 assign(irt_rM, getIRegT(rM));
18240 DIP("revsh r%u, r%u\n", rD, rM);
18273 /* ---------------- BX rM ---------------- */
18277 UInt rM = (INSN0(6,6) << 3) | INSN0(5,3);
18284 if (rM <= 14) {
18285 assign( dst, getIRegT(rM) );
18287 vassert(rM == 15);
18291 dres.jk_StopHere = rM == 14 ? Ijk_Ret : Ijk_Boring;
18293 DIP("bx r%u (possibly switch to ARM mode)\n", rM);
18299 /* ---------------- BLX rM ---------------- */
18300 /* Branch and link to interworking address in rM. */
18303 UInt rM = (INSN0(6,6) << 3) | INSN0(5,3);
18305 if (rM <= 14) {
18311 assign( dst, getIRegT(rM) );
18317 DIP("blx r%u (possibly switch to ARM mode)\n", rM);
18358 /* ---------------- ADD(HI) Rd, Rm ---------------- */
18361 UInt rM = (h2 << 3) | INSN0(5,3);
18364 if (rD == 15 && rM == 15) {
18368 assign( res, binop(Iop_Add32, getIRegT(rD), getIRegT(rM) ));
18383 DIP("add(hi) r%u, r%u\n", rD, rM);
18390 /* ---------------- CMP(HI) Rd, Rm ---------------- */
18393 UInt rM = (h2 << 3) | INSN0(5,3);
18399 assign( argR, getIRegT(rM) );
18402 DIP("cmphi r%u, r%u\n", rN, rM);
18409 /* ---------------- MOV(HI) Rd, Rm ---------------- */
18412 UInt rM = (h2 << 3) | INSN0(5,3);
18415 Rm are "low" registers, but newer versions allow it. */
18418 assign( val, getIRegT(rM) );
18430 dres.jk_StopHere = rM == 14 ? Ijk_Ret : Ijk_Boring;
18433 DIP("mov r%u, r%u\n", rD, rM);
18669 /* ---------------- ADDS Rd, Rn, Rm ---------------- */
18670 /* ---------------- SUBS Rd, Rn, Rm ---------------- */
18671 UInt rM = INSN0(8,6);
18678 assign( argR, getIRegT(rM) );
18684 DIP("%s r%u, r%u, r%u\n", isSub ? "subs" : "adds", rD, rN, rM);
18690 /* ------------- LDR Rd, [Rn, Rm] ------------- */
18691 /* ------------- STR Rd, [Rn, Rm] ------------- */
18692 /* LDR/STR Rd, [Rn + Rm] */
18695 UInt rM = INSN0(8,6);
18698 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
18709 DIP("%s r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
18715 /* ------------- LDRH Rd, [Rn, Rm] ------------- */
18716 /* ------------- STRH Rd, [Rn, Rm] ------------- */
18717 /* LDRH/STRH Rd, [Rn + Rm] */
18720 UInt rM = INSN0(8,6);
18723 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
18734 DIP("%sh r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
18739 /* ------------- LDRSH Rd, [Rn, Rm] ------------- */
18740 /* LDRSH Rd, [Rn + Rm] */
18743 UInt rM = INSN0(8,6);
18745 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
18752 DIP("ldrsh r%u, [r%u, r%u]\n", rD, rN, rM);
18757 /* ------------- LDRSB Rd, [Rn, Rm] ------------- */
18758 /* LDRSB Rd, [Rn + Rm] */
18761 UInt rM = INSN0(8,6);
18763 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
18770 DIP("ldrsb r%u, [r%u, r%u]\n", rD, rN, rM);
18776 /* ------------- LDRB Rd, [Rn, Rm] ------------- */
18777 /* ------------- STRB Rd, [Rn, Rm] ------------- */
18778 /* LDRB/STRB Rd, [Rn + Rm] */
18781 UInt rM = INSN0(8,6);
18784 IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
18795 DIP("%sb r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
19097 /* ---------------- LSLS Rd, Rm, #imm5 ---------------- */
19098 /* ---------------- LSRS Rd, Rm, #imm5 ---------------- */
19099 /* ---------------- ASRS Rd, Rm, #imm5 ---------------- */
19101 UInt rM = INSN0(5,3);
19108 assign(rMt, getIRegT(rM));
19115 dis_buf, &res, &resC, rMt, imm5, rM
19121 dis_buf, &res, &resC, rMt, imm5, rM
19127 dis_buf, &res, &resC, rMt, imm5, rM
19139 DIP("%ss r%u, r%u, #%u\n", wot, rD, rM, imm5);
19652 /* ---------- (T3) ADD{S}.W Rd, Rn, Rm, {shift} ---------- */
19653 /* ---------- (T3) SUB{S}.W Rd, Rn, Rm, {shift} ---------- */
19654 /* ---------- (T3) RSB{S}.W Rd, Rn, Rm, {shift} ---------- */
19662 UInt rM = INSN1(3,0);
19667 Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM);
19696 assign(rMt, getIRegT(rM));
19700 dis_buf, &argR, NULL, rMt, how, imm5, rM
19731 /* ---------- (T3) ADC{S}.W Rd, Rn, Rm, {shift} ---------- */
19732 /* ---------- (T2) SBC{S}.W Rd, Rn, Rm, {shift} ---------- */
19741 UInt rM = INSN1(3,0);
19742 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
19751 assign(rMt, getIRegT(rM));
19758 dis_buf, &argR, NULL, rMt, how, imm5, rM
19796 /* ---------- (T3) AND{S}.W Rd, Rn, Rm, {shift} ---------- */
19797 /* ---------- (T3) ORR{S}.W Rd, Rn, Rm, {shift} ---------- */
19798 /* ---------- (T3) EOR{S}.W Rd, Rn, Rm, {shift} ---------- */
19799 /* ---------- (T3) BIC{S}.W Rd, Rn, Rm, {shift} ---------- */
19800 /* ---------- (T1) ORN{S}.W Rd, Rn, Rm, {shift} ---------- */
19810 UInt rM = INSN1(3,0);
19811 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
19833 assign(rMt, getIRegT(rM));
19839 dis_buf, &argR, bS ? &oldC : NULL, rMt, how, imm5, rM
19865 /* -------------- (T?) LSL{S}.W Rd, Rn, Rm -------------- */
19866 /* -------------- (T?) LSR{S}.W Rd, Rn, Rm -------------- */
19867 /* -------------- (T?) ASR{S}.W Rd, Rn, Rm -------------- */
19868 /* -------------- (T?) ROR{S}.W Rd, Rn, Rm -------------- */
19875 UInt rM = INSN1(3,0);
19877 Bool valid = !isBadRegT(rN) && !isBadRegT(rM) && !isBadRegT(rD);
19887 assign(rMt, getIRegT(rM));
19890 rNt, how, rMt, rN, rM
19900 nm, bS ? "s" : "", rD, rN, rM);
19945 /* -------------- (T?) TST.W Rn, Rm, {shift} -------------- */
19946 /* -------------- (T?) TEQ.W Rn, Rm, {shift} -------------- */
19953 UInt rM = INSN1(3,0);
19954 if (!isBadRegT(rN) && !isBadRegT(rM)) {
19964 assign(rMt, getIRegT(rM));
19969 dis_buf, &argR, &oldC, rMt, how, imm5, rM
19986 /* -------------- (T3) CMP.W Rn, Rm, {shift} -------------- */
19987 /* -------------- (T2) CMN.W Rn, Rm, {shift} -------------- */
19994 UInt rM = INSN1(3,0);
19995 if (!isBadRegT(rN) && !isBadRegT(rM)) {
20004 assign(rMt, getIRegT(rM));
20008 dis_buf, &argR, NULL, rMt, how, imm5, rM
20279 op Rt, [Rn, Rm, LSL #imm8]
20314 UInt rM = INSN1(3,0);
20322 if (rN == 15 || isBadRegT(rT) || isBadRegT(rM))
20326 if (rN == 15 || isBadRegT(rM))
20353 binop(Iop_Shl32, getIRegT(rM), mkU8(imm2)) ));
20423 nm, rT, rN, rM, imm2);
20767 UInt rM = INSN1(3,0);
20769 if (bH/*ATC*/ || (rN != 13 && !isBadRegT(rM))) {
20779 bH ? binop(Iop_Shl32, getIRegT(rM), mkU8(1))
20780 : getIRegT(rM));
20801 bH ? 'h' : 'b', rN, rM, bH ? ", LSL #1" : "");
20861 UInt rM = INSN1(3,0);
20863 if (!isBadRegT(rD) && !isBadRegT(rM)) {
20868 assign(srcT, getIRegT(rM));
20920 DIP("%s r%u, r%u, ror #%u\n", nm, rD, rM, 8 * rot);
20925 /* -------------- MUL.W Rd, Rn, Rm -------------- */
20930 UInt rM = INSN1(3,0);
20931 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
20933 assign(res, binop(Iop_Mul32, getIRegT(rN), getIRegT(rM)));
20935 DIP("mul.w r%u, r%u, r%u\n", rD, rN, rM);
20940 /* -------------- SDIV.W Rd, Rn, Rm -------------- */
20945 UInt rM = INSN1(3,0);
20946 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
20951 assign(argR, getIRegT(rM));
20954 DIP("sdiv.w r%u, r%u, r%u\n", rD, rN, rM);
20959 /* -------------- UDIV.W Rd, Rn, Rm -------------- */
20964 UInt rM = INSN1(3,0);
20965 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
20970 assign(argR, getIRegT(rM));
20973 DIP("udiv.w r%u, r%u, r%u\n", rD, rN, rM);
20985 UInt rM = INSN1(3,0);
20987 && !isBadRegT(rN) && !isBadRegT(rM) && rDlo != rDhi) {
20990 getIRegT(rN), getIRegT(rM)));
20994 isU ? 'u' : 's', rDlo, rDhi, rN, rM);
21006 UInt rM = INSN1(3,0);
21008 && !isBadRegT(rM) && !isBadRegT(rA)) {
21014 binop(Iop_Mul32, getIRegT(rN), getIRegT(rM))));
21017 isMLA ? "mla" : "mls", rD, rN, rM, rA);
21047 UInt rM = INSN1(3,0);
21049 && !isBadRegT(rM) && rDhi != rDlo) {
21058 assign( argL, getIRegT(rM));
21069 isS ? 's' : 'u', rDlo, rDhi, rN, rM);
21079 UInt rM = INSN1(3,0);
21081 && !isBadRegT(rM) && rDhi != rDlo) {
21090 assign( argM, getIRegT(rM) );
21103 DIP("umaal r%u, r%u, r%u, r%u\n", rDlo, rDhi, rN, rM);
21115 UInt rM = INSN1(3,0);
21117 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
21121 binop(Iop_MullS32, getIRegT(rN), getIRegT(rM)),
21125 bitR ? "r" : "", rD, rN, rM);
21137 UInt rM = INSN1(3,0);
21139 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && (rA != 13)) {
21145 binop(Iop_MullS32, getIRegT(rN), getIRegT(rM))),
21149 bitR ? "r" : "", rD, rN, rM, rA);
21223 UInt rM = INSN1(3,0);
21225 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
21229 assign(srcR, getIRegT(rM));
21238 isU ? 'u' : 's', rD, rN, rM, rot);
21252 UInt rM = INSN1(3,0);
21254 if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
21258 assign(srcR, getIRegT(rM));
21267 isU ? 'u' : 's', rD, rN, rM, rot);
21609 UInt rM = INSN1(3,0);
21612 if (!isBadRegT(rM)) {
21613 DIP("pld%s [r%u, r%u, lsl %u]\n", bW ? "w" : "", rN, rM, imm2);
