Lines Matching defs:XT
332 /* Extract XT (destination register) field, instr[0,25:21] */
7486 UChar XT = ifieldRegXT( theInstr );
7489 DIP("mtvsrd vsr%d,r%u\n", XT, rA_addr);
7500 putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( rA ), mkU64( 0 ) ) );
7502 putVSReg( XT, binop( Iop_64HLtoV128,
7512 UChar XT = ifieldRegXT( theInstr );
7515 DIP("mtvsrwa vsr%d,r%u\n", XT, rA_addr);
7528 putVSReg( XT, binop( Iop_64HLtoV128,
7536 UChar XT = ifieldRegXT( theInstr );
7539 DIP("mtvsrwz vsr%d,r%u\n", rA_addr, XT);
7552 putVSReg( XT, binop( Iop_64HLtoV128,
12657 UChar XT = ifieldRegXT( theInstr );
12737 DIP("xscvdpsxds v%u,v%u\n", XT, XB);
12738 putVSReg( XT,
12745 DIP("xscvdpsxws v%u,v%u\n", XT, XB);
12746 putVSReg( XT,
12756 DIP("xscvdpuxds v%u,v%u\n", XT, XB);
12757 putVSReg( XT,
12767 DIP("xscvsxdsp v%u,v%u\n", XT, XB);
12768 putVSReg( XT,
12781 DIP("xscvsxddp v%u,v%u\n", XT, XB);
12782 putVSReg( XT,
12791 DIP("xscvuxdsp v%u,v%u\n", XT, XB);
12792 putVSReg( XT,
12805 DIP("xscvuxddp v%u,v%u\n", XT, XB);
12806 putVSReg( XT,
12819 DIP("xvcvdpsxws v%u,v%u\n", XT, XB);
12822 putVSReg( XT,
12843 DIP("xvcvsp%sxws v%u,v%u\n", un_signed ? "u" : "s", XT, XB);
12875 putVSReg( XT,
12883 DIP("xscvdpsp v%u,v%u\n", XT, XB);
12884 putVSReg( XT,
12897 DIP("xscvdpspn v%u,v%u\n", XT, XB);
12898 putVSReg( XT,
12909 DIP("xscvdpuxws v%u,v%u\n", XT, XB);
12910 putVSReg( XT,
12920 DIP("xscvspdp v%u,v%u\n", XT, XB);
12921 putVSReg( XT,
12929 DIP("xscvspdpn v%u,v%u\n", XT, XB);
12930 putVSReg( XT,
12939 DIP("xvcvdpsp v%u,v%u\n", XT, XB);
12940 putVSReg( XT,
12960 DIP("xvcvdpuxds v%u,v%u\n", XT, XB);
12961 putVSReg( XT,
12968 DIP("xvcvdpuxws v%u,v%u\n", XT, XB);
12969 putVSReg( XT,
12983 DIP("xvcvspdp v%u,v%u\n", XT, XB);
12984 putVSReg( XT,
12997 DIP("xvcvspsxds v%u,v%u\n", XT, XB);
12998 putVSReg( XT,
13011 DIP("xvcvspuxds v%u,v%u\n", XT, XB);
13012 putVSReg( XT,
13025 DIP("xvcvdpsxds v%u,v%u\n", XT, XB);
13026 putVSReg( XT,
13033 DIP("xvcvsxddp v%u,v%u\n", XT, XB);
13034 putVSReg( XT,
13047 DIP("xvcvuxddp v%u,v%u\n", XT, XB);
13048 putVSReg( XT,
13062 DIP("xvcvsxddp v%u,v%u\n", XT, XB);
13063 putVSReg( XT,
13086 DIP("xvcvuxddp v%u,v%u\n", XT, XB);
13087 putVSReg( XT,
13110 DIP("xvcvsxwdp v%u,v%u\n", XT, XB);
13111 putVSReg( XT,
13121 DIP("xvcvuxwdp v%u,v%u\n", XT, XB);
13122 putVSReg( XT,
13132 DIP("xvcvsxwsp v%u,v%u\n", XT, XB);
13133 putVSReg( XT, unop( Iop_I32StoFx4, getVSReg( XB ) ) );
13136 DIP("xvcvuxwsp v%u,v%u\n", XT, XB);
13137 putVSReg( XT, unop( Iop_I32UtoFx4, getVSReg( XB ) ) );
13155 UChar XT = ifieldRegXT( theInstr );
13205 DIP("xv%sdp v%d,v%d,v%d\n", oper_name, XT, XA, XB);
13213 putVSReg( XT,
13221 DIP("xvsqrtdp v%d,v%d\n", XT, XB);
13229 putVSReg( XT,
13238 /* xvm{add|sub}mdp XT,XA,XB is element-wise equivalent to fm{add|sub} FRT,FRA,FRC,FRB with . . .
13239 * XT == FRC
13244 * XT == FRB
13285 XT, XA, XB);
13286 assign(frT, unop(Iop_ReinterpI64asF64, unop(Iop_V128HIto64, getVSReg( XT ) ) ) );
13287 assign(frT2, unop(Iop_ReinterpI64asF64, unop(Iop_V128to64, getVSReg( XT ) ) ) );
13303 putVSReg( XT,
13398 UChar XT = ifieldRegXT( theInstr );
13419 DIP("xvaddsp v%d,v%d,v%d\n", XT, XA, XB);
13421 putVSReg( XT, triop(Iop_Add32Fx4, rm,
13426 DIP("xvmulsp v%d,v%d,v%d\n", XT, XA, XB);
13428 putVSReg( XT, triop(Iop_Mul32Fx4, rm,
13433 DIP("xvsubsp v%d,v%d,v%d\n", XT, XA, XB);
13435 putVSReg( XT, triop(Iop_Sub32Fx4, rm,
13449 DIP("xvdivsp v%d,v%d,v%d\n", XT, XA, XB);
13470 putVSReg( XT,
13478 DIP("xvsqrtsp v%d,v%d\n", XT, XB);
13503 putVSReg( XT,
13550 msp ? "msp" : "asp", XT, XA, XB);
13555 breakV128to4xF64( getVSReg( XT ), &t3, &t2, &t1, &t0 );
13590 putVSReg( XT,
14188 UChar XT = ifieldRegXT( theInstr );
14211 DIP("%s v%d,v%d\n", redp ? "xvredp" : "xvrsqrtedp", XT, XB);
14222 putVSReg( XT,
14259 DIP("%s v%d,v%d\n", resp ? "xvresp" : "xvrsqrtesp", XT, XB);
14297 putVSReg( XT,
14326 DIP("%s v%d,v%d v%d\n", isMin ? "xvminsp" : "xvmaxsp", XT, XA, XB);
14357 putVSReg( XT,
14377 DIP("%s v%d,v%d v%d\n", isMin ? "xvmindp" : "xvmaxdp", XT, XA, XB);
14378 putVSReg( XT, binop( Iop_64HLtoV128, get_max_min_fp(frA, frB, isMin), get_max_min_fp(frA2, frB2, isMin) ) );
14394 DIP("xvcpsgndp v%d,v%d,v%d\n", XT, XA, XB);
14395 putVSReg( XT,
14423 DIP("xvcpsgnsp v%d,v%d v%d\n",XT, XA, XB);
14461 putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( resHi ), mkexpr( resLo ) ) );
14475 DIP("xv%sabsdp v%d,v%d\n", make_negative ? "n" : "", XT, XB);
14484 putVSReg( XT, binop( Iop_64HLtoV128,
14521 putVSReg( XT,
14526 putVSReg( XT, mkexpr( absVal_vector ) );
14536 DIP("xvnegdp v%d,v%d\n", XT, XB);
14537 putVSReg( XT,
14561 DIP("xvrdpi%s v%d,v%d\n", _get_vsx_rdpi_suffix(opc2), XT, XB);
14562 putVSReg( XT,
14600 DIP("xvrspi%s v%d,v%d\n", insn_suffix, XT, XB);
14601 putVSReg( XT, unop( op, getVSReg(XB) ) );
14626 DIP("xvrspic v%d,v%d\n", XT, XB);
14627 putVSReg( XT,
14655 UChar XT = ifieldRegXT( theInstr );
14671 * of VSX[XT] are undefined after the operation; therefore, we can simply set
14676 DIP("xsaddsp v%d,v%d,v%d\n", XT, XA, XB);
14677 putVSReg( XT, binop( Iop_64HLtoV128,
14686 DIP("xssubsp v%d,v%d,v%d\n", XT, XA, XB);
14687 putVSReg( XT, binop( Iop_64HLtoV128,
14696 DIP("xsadddp v%d,v%d,v%d\n", XT, XA, XB);
14697 putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64,
14704 DIP("xsdivsp v%d,v%d,v%d\n", XT, XA, XB);
14705 putVSReg( XT, binop( Iop_64HLtoV128,
14714 DIP("xsdivdp v%d,v%d,v%d\n", XT, XA, XB);
14715 putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64,
14727 DIP("xsmadd%ssp v%d,v%d,v%d\n", mdp ? "m" : "a", XT, XA, XB);
14729 getVSReg( XT ) ) ) );
14730 putVSReg( XT,
14745 DIP("xsmadd%sdp v%d,v%d,v%d\n", mdp ? "m" : "a", XT, XA, XB);
14747 getVSReg( XT ) ) ) );
14748 putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64,
14762 DIP("xsmsub%ssp v%d,v%d,v%d\n", mdp ? "m" : "a", XT, XA, XB);
14764 getVSReg( XT ) ) ) );
14765 putVSReg( XT,
14780 DIP("xsmsub%sdp v%d,v%d,v%d\n", mdp ? "m" : "a", XT, XA, XB);
14782 getVSReg( XT ) ) ) );
14783 putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64,
14804 DIP("xsnmadd%sdp v%d,v%d,v%d\n", mdp ? "m" : "a", XT, XA, XB);
14806 getVSReg( XT ) ) ) );
14812 putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( getNegatedResult(maddResult) ),
14824 DIP("xsnmadd%ssp v%d,v%d,v%d\n", mdp ? "m" : "a", XT, XA, XB);
14826 getVSReg( XT ) ) ) );
14835 putVSReg( XT, binop( Iop_64HLtoV128,
14848 DIP("xsnmsub%ssp v%d,v%d,v%d\n", mdp ? "m" : "a", XT, XA, XB);
14850 getVSReg( XT ) ) ) );
14859 putVSReg( XT, binop( Iop_64HLtoV128,
14872 DIP("xsnmsub%sdp v%d,v%d,v%d\n", mdp ? "m" : "a", XT, XA, XB);
14874 getVSReg( XT ) ) ) );
14882 putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( getNegatedResult(msubResult) ), mkU64( 0 ) ) );
14888 DIP("xsmulsp v%d,v%d,v%d\n", XT, XA, XB);
14889 putVSReg( XT, binop( Iop_64HLtoV128,
14899 DIP("xsmuldp v%d,v%d,v%d\n", XT, XA, XB);
14900 putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64,
14907 DIP("xssubdp v%d,v%d,v%d\n", XT, XA, XB);
14908 putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64,
14916 DIP("xssqrtsp v%d,v%d\n", XT, XB);
14917 putVSReg( XT,
14927 DIP("xssqrtdp v%d,v%d\n", XT, XB);
14928 putVSReg( XT, binop( Iop_64HLtoV128, unop( Iop_ReinterpF64asI64,
14952 DIP("xstsqrtdp v%d,v%d\n", XT, XB);
15016 do_vvec_fp_cmp ( IRTemp vA, IRTemp vB, UChar XT, UChar flag_rC,
15072 putVSReg( XT,
15108 UChar XT = ifieldRegXT ( theInstr );
15127 XT, XA, XB);
15128 do_vvec_fp_cmp(vA, vB, XT, flag_rC, PPC_CMP_EQ);
15135 XT, XA, XB);
15136 do_vvec_fp_cmp(vA, vB, XT, flag_rC, PPC_CMP_GE);
15143 XT, XA, XB);
15144 do_vvec_fp_cmp(vA, vB, XT, flag_rC, PPC_CMP_GT);
15153 XT, XA, XB);
15155 putVSReg( XT, mkexpr(vD) );
15167 XT, XA, XB);
15169 putVSReg( XT, mkexpr(vD) );
15181 XT, XA, XB);
15183 putVSReg( XT, mkexpr(vD) );
15205 UChar XT = ifieldRegXT ( theInstr );
15220 * of VSX[XT] are undefined after the operation; therefore, we can simply
15227 /* Move abs val of dw 0 of VSX[XB] to dw 0 of VSX[XT]. */
15243 DIP("xsabsdp v%d,v%d\n", XT, XB);
15244 putVSReg(XT, mkexpr(absVal));
15253 DIP("xscpsgndp v%d,v%d v%d\n", XT, XA, XB);
15267 putVSReg(XT, mkexpr(vec_result));
15274 DIP("xsnabsdp v%d,v%d\n", XT, XB);
15279 putVSReg(XT, binop( Iop_64HLtoV128,
15291 DIP("xsnabsdp v%d,v%d\n", XT, XB);
15316 putVSReg( XT, mkexpr(vec_result));
15325 DIP("%s v%d,v%d v%d\n", isMin ? "xsmaxdp" : "xsmindp", XT, XA, XB);
15329 putVSReg( XT, binop( Iop_64HLtoV128, get_max_min_fp(frA, frB, isMin), mkU64( 0 ) ) );
15345 DIP("xsrdpi%s v%d,v%d\n", _get_vsx_rdpi_suffix(opc2), XT, XB);
15346 putVSReg( XT,
15362 DIP("%s v%d,v%d\n", redp ? "xsresp" : "xsrsqrtesp", XT,
15374 putVSReg( XT,
15396 DIP("%s v%d,v%d\n", redp ? "xsredp" : "xsrsqrtedp", XT, XB);
15406 putVSReg( XT,
15421 DIP("xsrsp v%d, v%d\n", XT, XB);
15426 putVSReg( XT, binop( Iop_64HLtoV128,
15450 UChar XT = ifieldRegXT ( theInstr );
15466 DIP("xxlxor v%d,v%d,v%d\n", XT, XA, XB);
15467 putVSReg( XT, binop( Iop_XorV128, mkexpr( vA ), mkexpr( vB ) ) );
15470 DIP("xxlor v%d,v%d,v%d\n", XT, XA, XB);
15471 putVSReg( XT, binop( Iop_OrV128, mkexpr( vA ), mkexpr( vB ) ) );
15474 DIP("xxlnor v%d,v%d,v%d\n", XT, XA, XB);
15475 putVSReg( XT, unop( Iop_NotV128, binop( Iop_OrV128, mkexpr( vA ),
15479 DIP("xxland v%d,v%d,v%d\n", XT, XA, XB);
15480 putVSReg( XT, binop( Iop_AndV128, mkexpr( vA ), mkexpr( vB ) ) );
15483 DIP("xxlandc v%d,v%d,v%d\n", XT, XA, XB);
15484 putVSReg( XT, binop( Iop_AndV128, mkexpr( vA ), unop( Iop_NotV128,
15488 DIP("xxlorc v%d,v%d,v%d\n", XT, XA, XB);
15489 putVSReg( XT, binop( Iop_OrV128,
15494 DIP("xxlnand v%d,v%d,v%d\n", XT, XA, XB);
15495 putVSReg( XT, unop( Iop_NotV128,
15500 DIP("xxleqv v%d,v%d,v%d\n", XT, XA, XB);
15501 putVSReg( XT, unop( Iop_NotV128,
15521 UChar XT = ifieldRegXT ( theInstr );
15540 DIP("lxsiwzx %d,r%u,r%u\n", XT, rA_addr, rB_addr);
15547 putVSReg( XT, binop( Iop_64HLtoV128,
15555 DIP("lxsiwax %d,r%u,r%u\n", XT, rA_addr, rB_addr);
15562 putVSReg( XT, binop( Iop_64HLtoV128,
15570 DIP("lxsspx %d,r%u,r%u\n", XT, rA_addr, rB_addr);
15580 putVSReg( XT, binop( Iop_64HLtoV128, exp, mkU64( 0 ) ) );
15586 DIP("lxsdx %d,r%u,r%u\n", XT, rA_addr, rB_addr);
15589 // we just performed is only a DW. But since the contents of VSR[XT] element 1
15591 putVSReg( XT, binop( Iop_64HLtoV128, exp, exp ) );
15600 DIP("lxvd2x %d,r%u,r%u\n", XT, rA_addr, rB_addr);
15605 putVSReg( XT, binop( Iop_64HLtoV128, high, low ) );
15611 DIP("lxvdsx %d,r%u,r%u\n", XT, rA_addr, rB_addr);
15613 putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( data ), mkexpr( data ) ) );
15620 DIP("lxvw4x %d,r%u,r%u\n", XT, rA_addr, rB_addr);
15638 putVSReg( XT, t0 );
15763 UChar XT = ifieldRegXT ( theInstr );
15791 DIP("xxsldwi v%d,v%d,v%d,%d\n", XT, XA, XB, SHW);
15792 putVSReg( XT, mkexpr(result) );
15813 DIP("xxpermdi v%d,v%d,v%d,0x%x\n", XT, XA, XB, DM);
15814 putVSReg( XT, mkexpr( vT ) );
15841 DIP("xxmrg%cw v%d,v%d,v%d\n", type, XT, XA, XB);
15842 putVSReg( XT, mkexpr( vT ) );
15850 DIP("xxsel v%d,v%d,v%d,v%d\n", XT, XA, XB, XC);
15852 putVSReg( XT, binop(Iop_OrV128,
15861 DIP("xxspltw v%d,v%d,%d\n", XT, XB, UIM);
15862 putVSReg( XT,
