Lines Matching full:vlo
1629 HReg vHi, vLo, vec;
1630 iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg);
1636 case Iop_V256to64_0: vec = vLo; off = -16; break;
1637 case Iop_V256to64_1: vec = vLo; off = -8; break;
3293 HReg vHi, vLo;
3294 iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg);
3295 return (e->Iex.Unop.op == Iop_V256toV128_1) ? vHi : vLo;
3754 HReg vLo = newVRegV(env);
3758 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, am0));
3761 *rLo = vLo;
3767 HReg vLo = newVRegV(env);
3771 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, am0));
3774 *rLo = vLo;
3783 HReg vLo = newVRegV(env);
3784 addInstr(env, mk_vMOVsd_RR(vHi, vLo));
3786 *rLo = vLo;
4233 HReg vLo = newVRegV(env);
4249 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, m16_rsp));
4251 *rLo = vLo;
4409 HReg vHi, vLo;
4410 iselDVecExpr(&vHi, &vLo, env, stmt->Ist.Store.data);
4411 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vLo, am0));
4465 HReg vHi, vLo;
4466 iselDVecExpr(&vHi, &vLo, env, stmt->Ist.Put.data);
4470 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vLo, am0));
