Lines Matching defs:rD
1137 Bool isLoad, HReg rD, ARMAMode1* amode ) {
1142 i->ARMin.LdSt32.rD = rD;
1149 HReg rD, ARMAMode2* amode ) {
1155 i->ARMin.LdSt16.rD = rD;
1161 Bool isLoad, HReg rD, ARMAMode1* amode ) {
1166 i->ARMin.LdSt8U.rD = rD;
1171 ARMInstr* ARMInstr_Ld8S ( ARMCondCode cc, HReg rD, ARMAMode2* amode ) {
1175 i->ARMin.Ld8S.rD = rD;
1504 ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) {
1511 i->ARMin.Alu.dst = rD;
1516 i->ARMin.Add32.rD = rD;
1585 ppHRegARM(i->ARMin.LdSt32.rD);
1593 ppHRegARM(i->ARMin.LdSt32.rD);
1603 ppHRegARM(i->ARMin.LdSt16.rD);
1612 ppHRegARM(i->ARMin.LdSt16.rD);
1619 ppHRegARM(i->ARMin.LdSt8U.rD);
1627 ppHRegARM(i->ARMin.LdSt8U.rD);
1635 ppHRegARM(i->ARMin.Ld8S.rD);
1972 ppHRegARM(i->ARMin.Add32.rD);
2040 addHRegUse(u, HRmWrite, i->ARMin.LdSt32.rD);
2042 addHRegUse(u, HRmRead, i->ARMin.LdSt32.rD);
2044 addHRegUse(u, HRmRead, i->ARMin.LdSt32.rD);
2050 addHRegUse(u, HRmWrite, i->ARMin.LdSt16.rD);
2052 addHRegUse(u, HRmRead, i->ARMin.LdSt16.rD);
2054 addHRegUse(u, HRmRead, i->ARMin.LdSt16.rD);
2060 addHRegUse(u, HRmWrite, i->ARMin.LdSt8U.rD);
2062 addHRegUse(u, HRmRead, i->ARMin.LdSt8U.rD);
2064 addHRegUse(u, HRmRead, i->ARMin.LdSt8U.rD);
2069 addHRegUse(u, HRmWrite, i->ARMin.Ld8S.rD);
2071 addHRegUse(u, HRmRead, i->ARMin.Ld8S.rD);
2291 addHRegUse(u, HRmWrite, i->ARMin.Add32.rD);
2343 i->ARMin.LdSt32.rD = lookupHRegRemap(m, i->ARMin.LdSt32.rD);
2347 i->ARMin.LdSt16.rD = lookupHRegRemap(m, i->ARMin.LdSt16.rD);
2351 i->ARMin.LdSt8U.rD = lookupHRegRemap(m, i->ARMin.LdSt8U.rD);
2355 i->ARMin.Ld8S.rD = lookupHRegRemap(m, i->ARMin.Ld8S.rD);
2489 i->ARMin.Add32.rD = lookupHRegRemap(m, i->ARMin.Add32.rD);
2799 static UInt* imm32_to_ireg ( UInt* p, Int rD, UInt imm32 )
2802 vassert(rD >= 0 && rD <= 14); // r15 not good to mess with!
2806 instr = XXXXXX__(X1110,X0011,X1010,X0000,rD,X0000);
2811 // ldr rD, [pc]
2812 instr = XXXXX___(X1110,X0101,X1001,X1111,rD);
2822 /* Generate movw rD, #low16. Then, if the high 16 are
2823 nonzero, generate movt rD, #high16. */
2826 instr = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
2831 instr = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
2843 instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
2846 rN = rD;
2851 instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
2854 rN = rD;
2859 instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
2862 rN = rD;
2867 instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
2870 rN = rD;
2881 static UInt* imm32_to_ireg_EXACTLY2 ( UInt* p, Int rD, UInt imm32 )
2884 /* Generate movw rD, #low16 ; movt rD, #high16. */
2888 instr = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
2892 instr = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
2904 static Bool is_imm32_to_ireg_EXACTLY2 ( UInt* p, Int rD, UInt imm32 )
2907 /* Generate movw rD, #low16 ; movt rD, #high16. */
2911 i0 = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
2914 i1 = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
2925 Bool isLoad, UInt rD, ARMAMode1* am )
2927 vassert(rD <= 12);
2943 rD);
2972 UInt rD = iregEnc(i->ARMin.Alu.dst);
2990 (subopc << 1) & 0xF, rN, rD);
3000 UInt rD = iregEnc(i->ARMin.Shift.dst);
3010 instr |= XXXXX__X(X1110,X0001,X1010,X0000,rD, /* _ _ */ rM);
3025 case ARMun_NEG: /* RSB rD,rS,#0 */
3070 HReg rD;
3077 rD = i->ARMin.LdSt32.rD;
3083 rD = i->ARMin.LdSt8U.rD;
3100 iregEnc(rD));
3110 HReg rD = i->ARMin.LdSt16.rD;
3134 iregEnc(rD), imm8hi, X1011, imm8lo);
3141 iregEnc(rD), imm8hi, X1011, imm8lo);
3148 iregEnc(rD), imm8hi, X1111, imm8lo);
3159 HReg rD = i->ARMin.Ld8S.rD;
3179 iregEnc(rD), imm8hi, X1101, imm8lo);
4594 UInt regD = iregEnc(i->ARMin.Add32.rD);
