Lines Matching refs:Race
125 threads. By the time we detect a race, the some of the elements of
274 race: program counter
292 XE_Race=1101, // race
324 } Race;
379 XS_Race=1201, /* race */
406 tl_assert(xe->XE.Race.thr);
407 xe->XE.Race.locksHeldW
410 xe->XE.Race.thr->locksetW,
424 HG_(describe_addr) (xe->XE.Race.data_addr, &xe->XE.Race.data_addrinfo);
432 Addr acc_addr = xe->XE.Race.data_addr;
433 Int acc_szB = xe->XE.Race.szB;
434 Thr* acc_thr = xe->XE.Race.thr->hbthr;
435 Bool acc_isW = xe->XE.Race.isWrite;
439 tl_assert(!xe->XE.Race.h2_ct_accEC);
440 tl_assert(!xe->XE.Race.h2_ct);
449 xe->XE.Race.h2_ct_accEC = wherep;
450 xe->XE.Race.h2_ct = threadp;
451 xe->XE.Race.h2_ct_accSzB = (Int)conf_szB;
452 xe->XE.Race.h2_ct_accIsW = conf_isW;
453 xe->XE.Race.h2_ct_locksHeldW
463 tl_assert( (!!xe->XE.Race.h2_ct) == (!!xe->XE.Race.h2_ct_accEC) );
486 if (0) VG_(printf)("XXXXXXXXX RACE on %#lx %s\n",
499 xe.XE.Race.data_addr = data_addr;
500 xe.XE.Race.szB = szB;
501 xe.XE.Race.isWrite = isWrite;
502 xe.XE.Race.thr = thr;
508 xe.XE.Race.data_addrinfo.tag = Addr_Undescribed;
515 xe.XE.Race.h2_ct_accSzB = 0;
516 xe.XE.Race.h2_ct_accIsW = False;
517 xe.XE.Race.h2_ct_accEC = NULL;
518 xe.XE.Race.h2_ct = NULL;
522 xe.XE.Race.h1_ct = h1_ct;
523 xe.XE.Race.h1_ct_mbsegstartEC = h1_ct_segstart;
524 xe.XE.Race.h1_ct_mbsegendEC = h1_ct_mbsegendEC;
671 return xe1->XE.Race.szB == xe2->XE.Race.szB
672 && xe1->XE.Race.isWrite == xe2->XE.Race.isWrite
674 ? xe1->XE.Race.data_addr == xe2->XE.Race.data_addr
892 announce_one_thread( xe->XE.Race.thr );
893 if (xe->XE.Race.h2_ct)
894 announce_one_thread( xe->XE.Race.h2_ct );
895 if (xe->XE.Race.h1_ct)
896 announce_one_thread( xe->XE.Race.h1_ct );
897 if (xe->XE.Race.data_addrinfo.Addr.Block.alloc_tinfo.tnr) {
901 == xe->XE.Race.data_addrinfo.Addr.Block.alloc_tinfo.tnr) {
1164 what = xe->XE.Race.isWrite ? "write" : "read";
1165 szB = xe->XE.Race.szB;
1168 tl_assert( HG_(is_sane_Thread)( xe->XE.Race.thr ));
1169 if (xe->XE.Race.h2_ct)
1170 tl_assert( HG_(is_sane_Thread)( xe->XE.Race.h2_ct ));
1176 emit( " <text>Possible data race during %s of size %d "
1178 what, szB, (void*)err_ga, (Int)xe->XE.Race.thr->errmsg_index );
1180 (Int)xe->XE.Race.thr->errmsg_index );
1184 if (xe->XE.Race.h2_ct) {
1185 tl_assert(xe->XE.Race.h2_ct_accEC); // assured by update_extra
1189 xe->XE.Race.h2_ct_accIsW ? "write" : "read",
1190 xe->XE.Race.h2_ct_accSzB,
1191 xe->XE.Race.h2_ct->errmsg_index );
1193 xe->XE.Race.h2_ct->errmsg_index);
1195 VG_(pp_ExeContext)( xe->XE.Race.h2_ct_accEC );
1198 if (xe->XE.Race.h1_ct) {
1202 xe->XE.Race.h1_ct->errmsg_index );
1204 xe->XE.Race.h1_ct->errmsg_index );
1206 if (xe->XE.Race.h1_ct_mbsegstartEC) {
1207 VG_(pp_ExeContext)( xe->XE.Race.h1_ct_mbsegstartEC );
1212 if (xe->XE.Race.h1_ct_mbsegendEC) {
1213 VG_(pp_ExeContext)( xe->XE.Race.h1_ct_mbsegendEC );
1222 announce_combined_LockP_vecs( xe->XE.Race.locksHeldW,
1223 xe->XE.Race.h2_ct_locksHeldW );
1225 emit( "Possible data race during %s of size %d "
1227 what, szB, (void*)err_ga, (Int)xe->XE.Race.thr->errmsg_index );
1229 tl_assert(xe->XE.Race.locksHeldW);
1230 show_LockP_summary_textmode( xe->XE.Race.locksHeldW, "" );
1233 if (xe->XE.Race.h2_ct) {
1234 tl_assert(xe->XE.Race.h2_ct_accEC); // assured by update_extra
1235 tl_assert(xe->XE.Race.h2_ct_locksHeldW);
1239 xe->XE.Race.h2_ct_accIsW ? "write" : "read",
1240 xe->XE.Race.h2_ct_accSzB,
1241 xe->XE.Race.h2_ct->errmsg_index );
1242 show_LockP_summary_textmode( xe->XE.Race.h2_ct_locksHeldW, "" );
1243 VG_(pp_ExeContext)( xe->XE.Race.h2_ct_accEC );
1246 if (xe->XE.Race.h1_ct) {
1249 xe->XE.Race.h1_ct->errmsg_index );
1250 if (xe->XE.Race.h1_ct_mbsegstartEC) {
1251 VG_(pp_ExeContext)( xe->XE.Race.h1_ct_mbsegstartEC );
1256 if (xe->XE.Race.h1_ct_mbsegendEC) {
1257 VG_(pp_ExeContext)( xe->XE.Race.h1_ct_mbsegendEC );
1264 VG_(pp_addrinfo) (err_ga, &xe->XE.Race.data_addrinfo);
1317 case XE_Race: return "Race";
1335 TRY("Race", XS_Race);
