Lines Matching refs:Operand
310 // Operand.
311 Operand::Operand(int64_t immediate)
319 Operand::Operand(Register reg, Shift shift, unsigned shift_amount)
331 Operand::Operand(Register reg, Extend extend, unsigned shift_amount)
345 bool Operand::IsImmediate() const {
350 bool Operand::IsShiftedRegister() const {
355 bool Operand::IsExtendedRegister() const {
360 bool Operand::IsZero() const {
369 Operand Operand::ToExtendedRegister() const {
372 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
410 MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode)
896 const Operand& operand) {
897 AddSub(rd, rn, operand, LeaveFlags, ADD);
903 const Operand& operand) {
904 AddSub(rd, rn, operand, SetFlags, ADD);
909 const Operand& operand) {
911 adds(zr, rn, operand);
917 const Operand& operand) {
918 AddSub(rd, rn, operand, LeaveFlags, SUB);
924 const Operand& operand) {
925 AddSub(rd, rn, operand, SetFlags, SUB);
929 void Assembler::cmp(const Register& rn, const Operand& operand) {
931 subs(zr, rn, operand);
935 void Assembler::neg(const Register& rd, const Operand& operand) {
937 sub(rd, zr, operand);
941 void Assembler::negs(const Register& rd, const Operand& operand) {
943 subs(rd, zr, operand);
949 const Operand& operand) {
950 AddSubWithCarry(rd, rn, operand, LeaveFlags, ADC);
956 const Operand& operand) {
957 AddSubWithCarry(rd, rn, operand, SetFlags, ADC);
963 const Operand& operand) {
964 AddSubWithCarry(rd, rn, operand, LeaveFlags, SBC);
970 const Operand& operand) {
971 AddSubWithCarry(rd, rn, operand, SetFlags, SBC);
975 void Assembler::ngc(const Register& rd, const Operand& operand) {
977 sbc(rd, zr, operand);
981 void Assembler::ngcs(const Register& rd, const Operand& operand) {
983 sbcs(rd, zr, operand);
990 const Operand& operand) {
991 Logical(rd, rn, operand, AND);
997 const Operand& operand) {
998 Logical(rd, rn, operand, ANDS);
1003 const Operand& operand) {
1004 ands(AppropriateZeroRegFor(rn), rn, operand);
1010 const Operand& operand) {
1011 Logical(rd, rn, operand, BIC);
1017 const Operand& operand) {
1018 Logical(rd, rn, operand, BICS);
1024 const Operand& operand) {
1025 Logical(rd, rn, operand, ORR);
1031 const Operand& operand) {
1032 Logical(rd, rn, operand, ORN);
1038 const Operand& operand) {
1039 Logical(rd, rn, operand, EOR);
1045 const Operand& operand) {
1046 Logical(rd, rn, operand, EON);
1207 const Operand& operand,
1210 ConditionalCompare(rn, operand, nzcv, cond, CCMN);
1215 const Operand& operand,
1218 ConditionalCompare(rn, operand, nzcv, cond, CCMP);
2528 // second operand of zero. Otherwise, orr with first operand zr is
2538 void Assembler::mvn(const Register& rd, const Operand& operand) {
2539 orn(rd, AppropriateZeroRegFor(rd), operand);
4609 const Operand& operand,
4613 if (operand.IsImmediate()) {
4614 int64_t immediate = operand.immediate();
4619 } else if (operand.IsShiftedRegister()) {
4620 VIXL_ASSERT(operand.reg().size() == rd.size());
4621 VIXL_ASSERT(operand.shift() != ROR);
4628 // or their 64-bit register equivalents, convert the operand from shifted to
4632 DataProcExtendedRegister(rd, rn, operand.ToExtendedRegister(), S,
4635 DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op);
4638 VIXL_ASSERT(operand.IsExtendedRegister());
4639 DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op);
4646 const Operand& operand,
4650 VIXL_ASSERT(rd.size() == operand.reg().size());
4651 VIXL_ASSERT(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
4652 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd));
4677 const Operand operand,
4680 if (operand.IsImmediate()) {
4681 int64_t immediate = operand.immediate();
4703 VIXL_ASSERT(operand.IsShiftedRegister());
4704 VIXL_ASSERT(operand.reg().size() == rd.size());
4706 DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op);
4726 const Operand& operand,
4731 if (operand.IsImmediate()) {
4732 int64_t immediate = operand.immediate();
4737 VIXL_ASSERT(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
4738 ccmpop = ConditionalCompareRegisterFixed | op | Rm(operand.reg());
4883 const Operand& operand,
4886 VIXL_ASSERT(operand.IsShiftedRegister());
4888 is_uint5(operand.shift_amount())));
4890 ShiftDP(operand.shift()) | ImmDPShift(operand.shift_amount()) |
4891 Rm(operand.reg()) | Rn(rn) | Rd(rd));
4897 const Operand& operand,
4901 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) |
4902 ExtendMode(operand.extend()) | ImmExtendShift(operand.shift_amount()) |
