Lines Matching full:constraint
7222 #define constraint(expr, err) \
7398 constraint (!inst.operands[i].isreg,
7448 constraint ((inst.operands[i].imm == REG_PC
7475 constraint ((is_t || inst.operands[i].writeback),
7513 constraint ((inst.operands[i].imm == REG_PC
7516 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
7524 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
8000 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
8028 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
8029 constraint (((inst.reloc.exp.X_op != O_constant
8111 constraint (msb > 32, _("bit-field extends past end of register"));
8130 constraint (msb > 32, _("bit-field extends past end of register"));
8142 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
8171 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
8236 constraint (inst.cond != COND_ALWAYS, BAD_COND);
8363 constraint (Rd == REG_SP, BAD_SP);
8369 constraint (Rd == REG_PC, BAD_PC);
8426 constraint (Rd == REG_PC, BAD_PC);
8427 constraint (Rn == REG_PC, BAD_PC);
8464 constraint ((Rd == REG_PC), BAD_PC);
8465 constraint ((Rn == REG_PC), BAD_PC);
8466 constraint ((Rm == REG_PC), BAD_PC);
8565 constraint (inst.operands[0].reg % 2 != 0,
8567 constraint (inst.operands[1].present
8570 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8571 constraint (!inst.operands[2].isreg, _("'[' expected"));
8601 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8619 constraint (inst.reloc.exp.X_op != O_constant
8623 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8633 constraint (inst.operands[0].reg % 2 != 0,
8635 constraint (inst.operands[1].present
8640 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8651 constraint (!(inst.operands[1].immisreg)
8676 constraint (inst.reloc.exp.X_op != O_constant
8693 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8708 constraint (inst.reloc.exp.X_op != O_constant
8760 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8762 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8857 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8869 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8902 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
9002 constraint (!inst.operands[0].isreg,
9004 constraint (inst.operands[0].postind,
9006 constraint (inst.operands[0].writeback,
9008 constraint (!inst.operands[0].preind,
9017 constraint (!inst.operands[0].isreg,
9019 constraint (inst.operands[0].postind,
9021 constraint (inst.operands[0].writeback,
9023 constraint (!inst.operands[0].preind,
9129 constraint (inst.operands[2].shifted,
9211 constraint (reg != REG_SP, _("SRS base register must be r13"));
9227 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
9235 constraint (inst.operands[0].reg == inst.operands[1].reg
9238 constraint (inst.reloc.exp.X_op != O_constant
9251 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
9257 constraint (inst.operands[0].reg == inst.operands[1].reg
9266 constraint (inst.operands[1].reg % 2 != 0,
9268 constraint (inst.operands[2].present
9273 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
9275 constraint (inst.operands[0].reg == inst.operands[1].reg
9289 constraint (inst.operands[0].reg == inst.operands[1].reg
9298 constraint (inst.operands[0].reg == inst.operands[1].reg
9384 constraint (inst.operands[2].imm != 2,
9401 constraint (inst.operands[0].imm != 2,
9429 constraint (ldstm_type != VFP_LDSTMIA,
9444 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
9634 constraint (inst.reloc.exp.X_op != O_constant
9660 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9739 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9794 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9924 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9941 constraint (inst.operands[i].immisreg,
9948 constraint (inst.reloc.exp.X_op != O_constant,
9951 constraint (value > 32
9980 constraint (!inst.operands[i].isreg,
9986 constraint (is_pc, BAD_PC_ADDRESSING);
9987 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9988 constraint (inst.operands[i].negative,
9990 constraint (inst.operands[i].postind,
9992 constraint (inst.operands[i].writeback,
9994 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
10000 constraint (inst.reloc.exp.X_op != O_constant,
10002 constraint (inst.reloc.exp.X_add_number < 0
10011 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
10012 constraint (is_t && inst.operands[i].writeback,
10014 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
10034 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
10035 constraint (is_t, _("cannot use post-indexing with this instruction"));
10168 constraint (Rd == REG_PC, BAD_PC);
10208 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
10239 constraint (inst.size_req == 2, BAD_HIREG);
10246 constraint (add, BAD_PC);
10247 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
10249 constraint (inst.reloc.exp.X_op != O_constant,
10251 constraint (inst.reloc.exp.X_add_number < 0
10323 constraint (Rd == REG_PC, BAD_PC);
10324 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
10325 constraint (Rs == REG_PC, BAD_PC);
10329 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
10334 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
10336 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
10343 constraint (inst.instruction == T_MNEM_adds
10349 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
10361 constraint (inst.operands[2].shifted, _("unshifted register required"));
10367 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
10376 constraint (1, _("dest must overlap one source register"));
10483 constraint (inst.operands[2].shifted
10497 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10499 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10501 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10502 constraint (Rd != Rs,
10580 constraint (inst.operands[2].shifted
10594 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10596 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10598 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10608 constraint (1, _("dest must overlap one source register"));
10617 constraint (msb > 32, _("bit-field extends past end of register"));
10648 constraint
10669 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10695 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10771 constraint (inst.cond != COND_ALWAYS,
10775 constraint (inst.operands[0].imm > range,
10885 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10889 constraint (inst.operands[1].present || inst.size_req == 4,
10919 constraint (inst.operands[0].reg > 7, BAD_HIREG);
11070 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11072 constraint (inst.operands[1].writeback,
11164 constraint (inst.operands[0].reg > 7
11166 constraint (inst.instruction != T_MNEM_ldmia
11197 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
11203 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
11215 constraint (inst.operands[0].reg == REG_LR,
11220 constraint (inst.operands[0].reg == inst.operands[1].reg,
11325 constraint (inst.operands[1].writeback == 1
11336 constraint (inst.operands[0].reg > 7, BAD_HIREG);
11341 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
11342 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
11355 constraint (!inst.operands[1].preind
11361 constraint (inst.instruction & 0x0600,
11363 constraint (inst.operands[1].reg == REG_PC
11366 constraint (inst.operands[1].immisreg,
11381 constraint (inst.operands[1].reg > 7, BAD_HIREG);
11392 constraint (inst.operands[1].imm > 7, BAD_HIREG);
11393 constraint (inst.operands[1].negative,
11421 constraint (inst.operands[0].reg == REG_LR,
11423 constraint (inst.operands[0].reg == REG_R12,
11528 constraint (Rn == REG_PC, BAD_PC);
11537 constraint (Rm == REG_PC, BAD_PC);
11566 constraint (Rn == REG_PC, BAD_PC);
11567 constraint (Rm == REG_PC, BAD_PC);
11568 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11704 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11748 constraint (inst.operands[1].shifted,
11776 constraint (Rn > 7,
11793 constraint (top, _(":lower16: not allowed this instruction"));
11798 constraint (!top, _(":upper16: not allowed this instruction"));
11826 constraint (Rn == REG_PC, BAD_PC);
11871 constraint (inst.operands[1].shifted
11883 constraint (inst.instruction > 0xffff
11885 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11887 constraint (Rn > 7 || Rm > 7,
11924 /* PR gas/12698: The constraint is only applied for m_profile.
11928 constraint ((flags != 0) && m_profile, _("selected processor does "
11934 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11952 constraint (!inst.operands[1].isreg,
11964 /* PR gas/12698: The constraint is only applied for m_profile.
11968 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11976 constraint ((flags & 0xff) != 0, _("selected processor does not support "
12017 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
12018 constraint (Rn > 7 || Rm > 7,
12034 constraint (1, _("dest must overlap one source register"));
12038 constraint (inst.instruction != T_MNEM_mul,
12103 constraint (inst.operands[0].present,
12140 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
12142 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
12177 constraint (inst.operands[2].shifted
12203 constraint (inst.reloc.exp.X_op != O_constant,
12241 constraint (inst.operands[0].writeback,
12243 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
12449 constraint (inst.operands[2].shifted,
12481 constraint (inst.operands[2].shifted,
12501 constraint (inst.operands[0].reg > 7
12503 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
12507 constraint (inst.operands[2].reg > 7, BAD_HIREG);
12508 constraint (inst.operands[0].reg != inst.operands[1].reg,
12524 constraint (inst.operands[2].shifted,
12584 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12586 constraint (inst.reloc.exp.X_op != O_constant,
12627 constraint (inst.reloc.exp.X_op != O_constant,
12632 constraint (shift_amount > 31,
12669 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12675 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12689 constraint (inst.operands[0].reg == inst.operands[1].reg
12749 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12751 constraint (1, BAD_HIREG);
12780 constraint (inst.operands[0].immisreg,
12786 constraint (Rn == REG_SP, BAD_SP);
12789 constraint (!half && inst.operands[0].shifted,
12802 constraint (inst.size_req == 2,
13122 the type constraint. */
13688 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
14269 constraint (inst.operands[0].reg != inst.operands[1].reg,
14362 /* This version only allow D registers, but that constraint is enforced during
14721 constraint (imm < 0 || (unsigned)imm >= et.size,
14733 constraint (imm < 1 || (unsigned)imm > et.size,
14745 constraint (imm < 0 || (unsigned)imm >= et.size,
14802 constraint (imm < 1 || (unsigned)imm > et.size,
14829 constraint (imm < 1 || (unsigned)imm > et.size,
14866 constraint (imm < 1 || (unsigned)imm > et.size,
15000 constraint (inst.operands[0].reg != inst.operands[1].reg,
15347 constraint (et.type == NT_invtype,
15357 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
15540 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
15566 constraint (et.size >= elsize,
15744 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15746 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15748 constraint (et.type == NT_invtype, _("bad type for scalar"));
15749 constraint (x >= 64 / et.size, _("scalar index out of range"));
15772 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15804 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15806 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15808 constraint (et.type == NT_invtype, _("bad type for scalar"));
15809 constraint (x >= 64 / et.size, _("scalar index out of range"));
15831 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15871 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15879 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15913 constraint (imm < 1 || (unsigned)imm > et.size,
16055 constraint (is_dbmode && !inst.operands[0].writeback,
16058 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
16166 constraint (typebits == -1, _("bad list type for instruction"));
16167 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
16228 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
16230 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
16232 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
16266 constraint (inst.operands[1].immisalign,
16333 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
16341 constraint (inst.operands[1].immisalign,
16343 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
16357 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
16381 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16413 constraint (!inst.operands[1].immisreg,
16415 constraint (postreg == 0xd || postreg == 0xf,
16421 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
16422 constraint (inst.reloc.exp.X_op != O_constant
