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17    along with GAS; see the file COPYING.  If not, write to the Free
34 point to a descriptor of the field, in which case our
35 md_number_to_field() routine gets called to process it.
38 assembler) return a pointer to the fixS in question. And I made it a
40 of a pointer to another structure: 80960 displacements are ALWAYS
44 directives for this size displacement have to be generated.
45 But the base assembler had to be modified to issue error
46 messages if the symbol did turn out to be external.
54 never is). The i80960 version of the linker needs a mod to
58 MEMA formats are always promoted to MEMB (32-bit) if the displacement
134 a line. If the line seems to have the form '# 123 filename'
146 /* Chars that can be used to separate mant from exp in floating point nums. */
153 /* Table used by base assembler to relax addresses based on varying length
157 3) how many bytes this mode will add to the size of the current frag
158 4) which index into the table to try if we can't fit into this one.
173 has to support. The fields are:
175 function to call to execute this pseudo-op
176 integer arg to pass to the function. */
180 /* Macros to extract info from an 'expressionS' structure 'e'. */
186 #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch. */
187 #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch. */
208 /* These masks are used to build up a set of MEMB mode bits. */
231 /* The two pieces of info we need to generate a register operand. */
282 use only: they are scaled back to range [0-31] for binary output. */
319 use only: they are scaled back to [0-3] for binary output. */
406 of branches taken/not-taken for later input to a utility that will
413 (1) before and after each conditional branch, a call to an external
415 counter itself, initialized to 0, immediately follows the call
427 (2) a table of pointers to the instrumented branches, so that an
429 the table begins with a 2-word header: a pointer to the next in
430 a linked list of such tables (initialized to 0); and a count
433 Note that input source code is expected to already contain calls
437 /* Number of branches instrumented so far. Also used to generate
442 /* Basename of local labels on instrumented branches, to avoid
450 /* Name of the table of pointers to branches. A local (i.e.,
489 Use base assembler's expression parser to parse an expression.
490 It, unfortunately, runs off a global which we have to save/restore
491 in order to make it work for us.
499 parse_expr (char *textP, /* Text of expression to be parsed. */
500 expressionS *expP) /* Where to put the results of parsing. */
537 Return pointer to where it was placed. */
540 emit (long instr) /* Word to be output, host byte order. */
542 char *toP; /* Where to output it. */
545 md_number_to_chars (toP, instr, 4); /* Convert to target byte order. */
555 o an address fixup to be done when all symbol values are known, or
557 will be done for cobr instructions that may have to be relaxed
558 in to compare/branch instructions (8 bytes) if the final
572 char *outP; /* Where instruction binary is output to. */
608 /* We want to modify a bit field when the address is
610 bit_fix structure. So we're going to lie and store
616 as_bad (_("attempt to branch into different segment"));
639 /* mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
648 mema_to_memb (char * opcodeP) /* Where to find the opcode, in target byte order. */
715 parse_regop (struct regop *regopP, /* Where to put description of register operand. */
807 Here, an "index specification" is taken to be anything surrounded
811 square brackets, and return a pointer to it. Otherwise, return NULL. */
814 get_ispec (char *textP) /* Pointer to memory operand from source instruction, no white space. */
817 /* Points to start of index specification. */
819 /* Points to end of index specification. */
857 things. Then at the end, if we go to MEMB format, we need only set
865 0101 Would seem to mean "abase-only" -- it means IP-relative.
866 Must be converted to 0100.
868 0110 Would seem to mean "index-only", but is reserved.
871 The other thing to observe is that we parse from the right, peeling
876 parse_memop (memS *memP, /* Where to put the results. */
877 char *argP, /* Text of the operand to be parsed. */
880 char *indexP; /* Pointer to index specification with "[]" removed. */
884 /* Scale factor: 1,2,4,8, or 16. Later converted to internal format
888 int *intP; /* Pointer to register number. */
944 /* Convert scale to its binary encoding. */
983 /* We have to specialcase ip-rel mode. */
1015 /* Go with MEMA instruction format for now (grow to MEMB later
1017 has a single mode bit: set it to indicate that abase is
1024 /* Go with MEMA instruction format for now (grow to MEMB later
1062 struct i960_opcode *oP,/* Pointer to description of instruction. */
1068 memS instr; /* Description of binary to be output. */
1069 char *outP; /* Where the binary was output to. */
1122 instruction to MEMB format, output
1140 may change at link time. We HAVE to reserve 32 bits.
1141 Convert already-output opcode to MEMB format. */
1195 Determine if a "shlo" instruction can be used to implement a "ldconst".
1196 This means that some number X < 32 can be shifted left to produce the
1211 /* Shift 'n' right until a 1 is about to be lost. */
1228 arg[2] name of register to be loaded
1237 int n; /* Constant to be loaded. */
1309 struct i960_opcode *oP)/* Pointer to description of instruction. */
1311 long instr; /* Binary to be output. */
1377 - all strings of whitespace have been collapsed to a single blank.
1381 args[0] is untouched. args[1] points to first operand, etc. All args:
1389 get_args (char *p, /* Pointer to comma-separated operands; Mucked by us. */
1390 char *args[]) /* Output arg: pointers to operands placed in args[1-3].
1395 char *to;
1409 to = p;
1424 *to++ = '\0'; /* Terminate argument. */
1425 args[++n] = to; /* Start next argument. */
1429 *to++ = *p++;
1431 *to = '\0';
1440 - all strings of whitespace have been collapsed to a single blank.
1443 args[0] points to opcode, other entries point to operands. All strings:
1452 i_scan (char *iP, /* Pointer to ascii instruction; Mucked by us. */
1453 char *args[]) /* Output arg: pointers to opcode and operands placed here.
1482 /* Emit call to "increment" routine. */
1484 /* Emit inline counter to be incremented. */
1498 ctrl_fmt (char *targP, /* Pointer to text of lone operand (if any). */
1502 int instrument; /* TRUE iff we should add instrumentation to track
1532 /* Pointer to description of instruction. */
1571 /* A third operand to a COBR is always a displacement. Parse
1587 - all white space compressed to single blanks
1599 /* Pointer to instruction description. */
1604 /* Setting of branch-prediction bit(s) to be OR'd into instruction
1634 /* We could check here to see if the target architecture
1659 /* Now generate a 'bno' to same arg */
1724 md_number_to_field (char *instrP, /* Pointer to instruction to be fixed. */
1726 bit_fixS *bfixP) /* Description of bit field to be fixed up. */
1728 int numbits; /* Length of bit field to be fixed. */
1729 long instr; /* 32-bit instruction to be fixed-up. */
1730 long sign; /* 0 or -1, according to sign bit of 'val'. */
1732 /* Convert instruction back to host byte order. */
1735 /* Surprise! -- we stored the number of bits to be modified rather
1736 than a pointer to a structure. */
1770 generate errors. The default is to replace each such
1777 Add code to collect information about branches taken, for
1795 The default is to generate code for any instruction or feature
1885 -b add code to collect statistics about branches taken\n\
1929 relax_cobr (fragS *fragP) /* fragP->fr_opcode is assumed to point to
1937 /* ->instruction to be replaced. */
1977 variable fragments according to how much relaxation was done.
1980 to reach the symbol in question. Set up an address fixup, but otherwise
2024 based on undefined symbols will have to be replaced with a compare
2031 /* If symbol is undefined in this segment, go to "relaxed" state
2045 This routine exists in order to overcome machine byte-order problems
2049 executable code is actually downloaded to the i80960). Therefore,
2085 The code emitted here would be functionally equivalent to the following
2091 .word 0 # link to next table
2102 /* Where the binary was output to. */
2112 emit (0); /* .word 0 #link to next table */
2128 arg[1]: name of 'call' entry point to leaf procedure
2129 arg[2]: name of 'bal' entry point to leaf procedure
2132 the first argument is taken to be the 'bal' entry point.
2142 symbolS *callP; /* Pointer to leafproc 'call' entry point symbol. */
2143 symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol. */
2183 arg[1]: name of entry point to system procedure
2189 by adding 1 to it. It must be unbiased before it is used. */
2228 and dispatches them to the correct handler. */
2237 char *p; /* Pointer to beginning of unparsed argument string. */
2242 /* Advance input pointer to end of line. */
2255 /* Dispatch to correct handler. */
2281 Check to see if the relocation involves a 'callj' instruction to a:
2290 to use the 'bal' entry point, and has substituted that symbol into the
2296 /* Points to the binary for the instruction being relocated. */
2311 /* Nothing else needs to be done for this instruction. Make
2318 as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy));
2356 /* We have no need to default values of symbols. */
2364 /* Exactly what point is a PC-relative offset relative TO?
2365 On the i960, they're relative to the address of the instruction,
2390 13-bit displacement and are only to be used
2465 /* Align an address by rounding it up to the specified boundary. */
2469 valueT addr) /* Address to be rounded up. */
2481 For coff, we cheat and store a pointer to the bal symbol in the
2574 /* The text section "ends" with another alignment reloc, to which we
2621 /* Translate internal representation of relocation info to BFD target
2624 FIXME: To what extent can we get all relevant targets to use this? */