Lines Matching refs:PROCESSOR_V850E2V3_UP
660 { "cfg", 7, PROCESSOR_V850E2V3_UP },
669 { "dpa0l", 16, PROCESSOR_V850E2V3_UP },
670 { "dpa0u", 17, PROCESSOR_V850E2V3_UP },
671 { "dpa1l", 18, PROCESSOR_V850E2V3_UP },
672 { "dpa1u", 19, PROCESSOR_V850E2V3_UP },
673 { "dpa2l", 20, PROCESSOR_V850E2V3_UP },
674 { "dpa2u", 21, PROCESSOR_V850E2V3_UP },
675 { "dpa3l", 22, PROCESSOR_V850E2V3_UP },
676 { "dpa3u", 23, PROCESSOR_V850E2V3_UP },
677 { "dpa4l", 24, PROCESSOR_V850E2V3_UP },
678 { "dpa4u", 25, PROCESSOR_V850E2V3_UP },
679 { "dpa5l", 26, PROCESSOR_V850E2V3_UP },
680 { "dpa5u", 27, PROCESSOR_V850E2V3_UP },
682 { "eh_base", 3, PROCESSOR_V850E2V3_UP },
683 { "eh_cfg", 1, PROCESSOR_V850E2V3_UP },
684 { "eh_reset", 2, PROCESSOR_V850E2V3_UP },
693 { "fpcc", 9, PROCESSOR_V850E2V3_UP },
694 { "fpcfg", 10, PROCESSOR_V850E2V3_UP },
695 { "fpec", 11, PROCESSOR_V850E2V3_UP },
696 { "fpepc", 7, PROCESSOR_V850E2V3_UP },
697 { "fpspc", 27, PROCESSOR_V850E2V3_UP },
698 { "fpsr", 6, PROCESSOR_V850E2V3_UP },
699 { "fpst", 8, PROCESSOR_V850E2V3_UP },
700 { "ipa0l", 6, PROCESSOR_V850E2V3_UP },
701 { "ipa0u", 7, PROCESSOR_V850E2V3_UP },
702 { "ipa1l", 8, PROCESSOR_V850E2V3_UP },
703 { "ipa1u", 9, PROCESSOR_V850E2V3_UP },
704 { "ipa2l", 10, PROCESSOR_V850E2V3_UP },
705 { "ipa2u", 11, PROCESSOR_V850E2V3_UP },
706 { "ipa3l", 12, PROCESSOR_V850E2V3_UP },
707 { "ipa3u", 13, PROCESSOR_V850E2V3_UP },
708 { "ipa4l", 14, PROCESSOR_V850E2V3_UP },
709 { "ipa4u", 15, PROCESSOR_V850E2V3_UP },
710 { "mca", 24, PROCESSOR_V850E2V3_UP },
711 { "mcc", 26, PROCESSOR_V850E2V3_UP },
712 { "mcr", 27, PROCESSOR_V850E2V3_UP },
713 { "mcs", 25, PROCESSOR_V850E2V3_UP },
714 { "mpc", 1, PROCESSOR_V850E2V3_UP },
715 { "mpm", 0, PROCESSOR_V850E2V3_UP },
716 { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3_UP },
717 { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3_UP },
718 { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3_UP },
719 { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3_UP },
720 { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3_UP },
721 { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3_UP },
722 { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3_UP },
723 { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3_UP },
724 { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3_UP },
725 { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3_UP },
726 { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3_UP },
727 { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3_UP },
728 { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3_UP },
729 { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3_UP },
730 { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3_UP },
731 { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3_UP },
732 { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3_UP },
733 { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3_UP },
734 { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3_UP },
735 { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3_UP },
736 { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3_UP },
737 { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3_UP },
738 { "mpu10_mpc", 1, PROCESSOR_V850E2V3_UP },
739 { "mpu10_mpm", 0, PROCESSOR_V850E2V3_UP },
740 { "mpu10_tid", 2, PROCESSOR_V850E2V3_UP },
741 { "mpu10_vmadr", 5, PROCESSOR_V850E2V3_UP },
742 { "mpu10_vmecr", 3, PROCESSOR_V850E2V3_UP },
743 { "mpu10_vmtid", 4, PROCESSOR_V850E2V3_UP },
744 { "pid", 6, PROCESSOR_V850E2V3_UP },
745 { "pmcr0", 4, PROCESSOR_V850E2V3_UP },
746 { "pmis2", 14, PROCESSOR_V850E2V3_UP },
748 { "scbp", 12, PROCESSOR_V850E2V3_UP },
749 { "sccfg", 11, PROCESSOR_V850E2V3_UP },
782 { "sw_base", 3, PROCESSOR_V850E2V3_UP },
783 { "sw_cfg", 1, PROCESSOR_V850E2V3_UP },
784 { "sw_ctl", 0, PROCESSOR_V850E2V3_UP },
785 { "tid", 2, PROCESSOR_V850E2V3_UP },
786 { "vmadr", 6, PROCESSOR_V850E2V3_UP },
787 { "vmecr", 4, PROCESSOR_V850E2V3_UP },
788 { "vmtid", 5, PROCESSOR_V850E2V3_UP },
789 { "vsadr", 2, PROCESSOR_V850E2V3_UP },
790 { "vsecr", 0, PROCESSOR_V850E2V3_UP },
791 { "vstid", 1, PROCESSOR_V850E2V3_UP },
830 { "eq", 0x2, PROCESSOR_V850E2V3_UP }, /* true. */
831 { "f", 0x0, PROCESSOR_V850E2V3_UP }, /* true. */
832 { "ge", 0xd, PROCESSOR_V850E2V3_UP }, /* false. */
833 { "gl", 0xb, PROCESSOR_V850E2V3_UP }, /* false. */
834 { "gle", 0x9, PROCESSOR_V850E2V3_UP }, /* false. */
835 { "gt", 0xf, PROCESSOR_V850E2V3_UP }, /* false. */
836 { "le", 0xe, PROCESSOR_V850E2V3_UP }, /* true. */
837 { "lt", 0xc, PROCESSOR_V850E2V3_UP }, /* true. */
838 { "neq", 0x2, PROCESSOR_V850E2V3_UP }, /* false. */
839 { "nge", 0xd, PROCESSOR_V850E2V3_UP }, /* true. */
840 { "ngl", 0xb, PROCESSOR_V850E2V3_UP }, /* true. */
841 { "ngle",0x9, PROCESSOR_V850E2V3_UP }, /* true. */
842 { "ngt", 0xf, PROCESSOR_V850E2V3_UP }, /* true. */
843 { "nle", 0xe, PROCESSOR_V850E2V3_UP }, /* false. */
844 { "nlt", 0xc, PROCESSOR_V850E2V3_UP }, /* false. */
845 { "oge", 0x5, PROCESSOR_V850E2V3_UP }, /* false. */
846 { "ogl", 0x3, PROCESSOR_V850E2V3_UP }, /* false. */
847 { "ogt", 0x7, PROCESSOR_V850E2V3_UP }, /* false. */
848 { "ole", 0x6, PROCESSOR_V850E2V3_UP }, /* true. */
849 { "olt", 0x4, PROCESSOR_V850E2V3_UP }, /* true. */
850 { "or", 0x1, PROCESSOR_V850E2V3_UP }, /* false. */
851 { "seq", 0xa, PROCESSOR_V850E2V3_UP }, /* true. */
852 { "sf", 0x8, PROCESSOR_V850E2V3_UP }, /* true. */
853 { "sne", 0xa, PROCESSOR_V850E2V3_UP }, /* false. */
854 { "st", 0x8, PROCESSOR_V850E2V3_UP }, /* false. */
855 { "t", 0x0, PROCESSOR_V850E2V3_UP }, /* false. */
856 { "ueq", 0x3, PROCESSOR_V850E2V3_UP }, /* true. */
857 { "uge", 0x4, PROCESSOR_V850E2V3_UP }, /* false. */
858 { "ugt", 0x6, PROCESSOR_V850E2V3_UP }, /* false. */
859 { "ule", 0x7, PROCESSOR_V850E2V3_UP }, /* true. */
860 { "ult", 0x5, PROCESSOR_V850E2V3_UP }, /* true. */
861 { "un", 0x1, PROCESSOR_V850E2V3_UP }, /* true. */
3107 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17)
3152 if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17)
