Lines Matching refs:PROCESSOR_V850E3V5_UP
870 { "cfald", 0x44, PROCESSOR_V850E3V5_UP },
871 { "cfali", 0x40, PROCESSOR_V850E3V5_UP },
872 { "chbid", 0x04, PROCESSOR_V850E3V5_UP },
873 { "chbii", 0x00, PROCESSOR_V850E3V5_UP },
874 { "chbiwbd", 0x06, PROCESSOR_V850E3V5_UP },
875 { "chbwbd", 0x07, PROCESSOR_V850E3V5_UP },
876 { "cibid", 0x24, PROCESSOR_V850E3V5_UP },
877 { "cibii", 0x20, PROCESSOR_V850E3V5_UP },
878 { "cibiwbd", 0x26, PROCESSOR_V850E3V5_UP },
879 { "cibwbd", 0x27, PROCESSOR_V850E3V5_UP },
880 { "cildd", 0x65, PROCESSOR_V850E3V5_UP },
881 { "cildi", 0x61, PROCESSOR_V850E3V5_UP },
882 { "cistd", 0x64, PROCESSOR_V850E3V5_UP },
883 { "cisti", 0x60, PROCESSOR_V850E3V5_UP },
891 { "prefd", 0x04, PROCESSOR_V850E3V5_UP },
892 { "prefi", 0x00, PROCESSOR_V850E3V5_UP },
900 { "vr0", 0, PROCESSOR_V850E3V5_UP },
901 { "vr1", 1, PROCESSOR_V850E3V5_UP },
902 { "vr10", 10, PROCESSOR_V850E3V5_UP },
903 { "vr11", 11, PROCESSOR_V850E3V5_UP },
904 { "vr12", 12, PROCESSOR_V850E3V5_UP },
905 { "vr13", 13, PROCESSOR_V850E3V5_UP },
906 { "vr14", 14, PROCESSOR_V850E3V5_UP },
907 { "vr15", 15, PROCESSOR_V850E3V5_UP },
908 { "vr16", 16, PROCESSOR_V850E3V5_UP },
909 { "vr17", 17, PROCESSOR_V850E3V5_UP },
910 { "vr18", 18, PROCESSOR_V850E3V5_UP },
911 { "vr19", 19, PROCESSOR_V850E3V5_UP },
912 { "vr2", 2, PROCESSOR_V850E3V5_UP },
913 { "vr20", 20, PROCESSOR_V850E3V5_UP },
914 { "vr21", 21, PROCESSOR_V850E3V5_UP },
915 { "vr22", 22, PROCESSOR_V850E3V5_UP },
916 { "vr23", 23, PROCESSOR_V850E3V5_UP },
917 { "vr24", 24, PROCESSOR_V850E3V5_UP },
918 { "vr25", 25, PROCESSOR_V850E3V5_UP },
919 { "vr26", 26, PROCESSOR_V850E3V5_UP },
920 { "vr27", 27, PROCESSOR_V850E3V5_UP },
921 { "vr28", 28, PROCESSOR_V850E3V5_UP },
922 { "vr29", 29, PROCESSOR_V850E3V5_UP },
923 { "vr3", 3, PROCESSOR_V850E3V5_UP },
924 { "vr30", 30, PROCESSOR_V850E3V5_UP },
925 { "vr31", 31, PROCESSOR_V850E3V5_UP },
926 { "vr4", 4, PROCESSOR_V850E3V5_UP },
927 { "vr5", 5, PROCESSOR_V850E3V5_UP },
928 { "vr6", 6, PROCESSOR_V850E3V5_UP },
929 { "vr7", 7, PROCESSOR_V850E3V5_UP },
930 { "vr8", 8, PROCESSOR_V850E3V5_UP },
931 { "vr9", 9, PROCESSOR_V850E3V5_UP },
3065 if (((processor_mask & PROCESSOR_V850E3V5_UP) == 0) || default_disp_size == 22)
