Lines Matching full:info
62 aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
66 insert_field (self->fields[0], code, info->reg.regno, 0);
74 aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
78 insert_field (self->fields[0], code, info->reglane.regno, inst->opcode->mask);
82 int pos = info->qualifier - AARCH64_OPND_QLF_S_B;
83 if (info->type == AARCH64_OPND_En
87 assert (info->idx == 1); /* Vn */
88 aarch64_insn value = info->reglane.index << pos;
100 aarch64_insn value = ((info->reglane.index << 1) | 1) << pos;
108 switch (info->qualifier)
112 insert_fields (code, info->reglane.index, 0, 3, FLD_M, FLD_L, FLD_H);
116 insert_fields (code, info->reglane.index, 0, 2, FLD_L, FLD_H);
120 insert_field (FLD_H, code, info->reglane.index, 0);
131 aarch64_ins_reglist (const aarch64_operand *self, const aarch64_opnd_info *info,
136 insert_field (self->fields[0], code, info->reglist.first_regno, 0);
138 insert_field (FLD_len, code, info->reglist.num_regs - 1, 0);
146 const aarch64_opnd_info *info, aarch64_insn *code,
154 insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
159 switch (info->reglist.num_regs)
169 value = info->reglist.num_regs == 4 ? 0x3 : 0x8;
189 const aarch64_opnd_info *info, aarch64_insn *code,
198 insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
201 if (is_ld1r && info->reglist.num_regs == 2)
214 const aarch64_opnd_info *info, aarch64_insn *code,
221 assert (info->reglist.has_index);
224 insert_field (FLD_Rt, code, info->reglist.first_regno, 0);
226 switch (info->qualifier)
230 QSsize = info->reglist.index;
235 QSsize = info->reglist.index << 1;
240 QSsize = info->reglist.index << 2;
245 QSsize = info->reglist.index << 3 | 0x1;
263 const aarch64_opnd_info *info,
266 unsigned val = aarch64_get_qualifier_standard_value (info->qualifier);
287 assert (info->type == AARCH64_OPND_IMM_VLSR
288 || info->type == AARCH64_OPND_IMM_VLSL);
290 if (info->type == AARCH64_OPND_IMM_VLSR)
298 imm = (16 << (unsigned)val) - info->imm.value;
307 imm = info->imm.value + (8 << (unsigned)val);
316 aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
324 imm = info->imm.value;
338 aarch64_ins_imm_half (const aarch64_operand *self, const aarch64_opnd_info *info,
342 aarch64_ins_imm (self, info, code, inst);
344 insert_field (FLD_hw, code, info->shifter.amount >> 4, 0);
352 const aarch64_opnd_info *info,
357 uint64_t imm = info->imm.value;
358 enum aarch64_modifier_kind kind = info->shifter.kind;
359 int amount = info->shifter.amount;
363 if (!info->imm.is_fp && aarch64_get_qualifier_esize (opnd0_qualifier) == 8)
409 aarch64_ins_fbits (const aarch64_operand *self, const aarch64_opnd_info *info,
413 insert_field (self->fields[0], code, 64 - info->imm.value, 0);
420 aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info,
424 aarch64_insn value = info->shifter.amount ? 1 : 0;
427 insert_field (self->fields[1], code, info->imm.value, 0);
434 aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
438 uint64_t imm = info->imm.value;
455 aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info,
460 assert (info->idx == 0);
463 aarch64_ins_regno (self, info, code, inst);
470 switch (info->qualifier)
482 value = aarch64_get_qualifier_standard_value (info->qualifier);
492 const aarch64_opnd_info *info, aarch64_insn *code,
496 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
504 const aarch64_opnd_info *info, aarch64_insn *code,
508 enum aarch64_modifier_kind kind = info->shifter.kind;
511 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
513 insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
519 if (info->qualifier != AARCH64_OPND_QLF_S_B)
520 S = info->shifter.amount != 0;
527 S = info->shifter.operator_present && info->shifter.amount_present;
536 const aarch64_opnd_info *info,
543 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
545 imm = info->addr.offset.imm;
548 imm >>= get_logsz (aarch64_get_qualifier_esize (info->qualifier));
551 if (info->addr.writeback)
557 assert (info->addr.preind != info->addr.postind);
558 if (info->addr.preind)
568 const aarch64_opnd_info *info,
572 int shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
575 insert_field (self->fields[0], code, info->addr.base_regno, 0);
577 insert_field (self->fields[1], code,info->addr.offset.imm >> shift, 0);
585 const aarch64_opnd_info *info, aarch64_insn *code,
589 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
591 if (info->addr.offset.is_reg)
592 insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
601 const aarch64_opnd_info *info, aarch64_insn *code,
605 insert_field (FLD_cond, code, info->cond->value, 0);
612 const aarch64_opnd_info *info, aarch64_insn *code,
616 insert_fields (code, info->sysreg, inst->opcode->mask, 5,
624 const aarch64_opnd_info *info, aarch64_insn *code,
628 insert_fields (code, info->pstatefield, inst->opcode->mask, 2,
636 const aarch64_opnd_info *info, aarch64_insn *code,
640 insert_fields (code, info->sysins_op->value, inst->opcode->mask, 4,
649 const aarch64_opnd_info *info, aarch64_insn *code,
653 insert_field (FLD_CRm, code, info->barrier->value, 0);
662 const aarch64_opnd_info *info, aarch64_insn *code,
666 insert_field (FLD_Rt, code, info->prfop->value, 0);
674 const aarch64_opnd_info *info, aarch64_insn *code,
680 insert_field (FLD_Rm, code, info->reg.regno, 0);
682 kind = info->shifter.kind;
684 kind = info->qualifier == AARCH64_OPND_QLF_W
688 insert_field (FLD_imm3, code, info->shifter.amount, 0);
697 const aarch64_opnd_info *info, aarch64_insn *code,
701 insert_field (FLD_Rm, code, info->reg.regno, 0);
704 aarch64_get_operand_modifier_value (info->shifter.kind), 0);
706 insert_field (FLD_imm6, code, info->shifter.amount, 0);
1267 aarch64_opnd_info *info = inst->operands;
1270 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++info)
1276 if (info->skip)
1283 aarch64_insert_operand (opnd, info, &inst->value, inst);
