1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_INSTRUCTION_CODES_H_ 6 #define V8_COMPILER_INSTRUCTION_CODES_H_ 7 8 #include <iosfwd> 9 10 #if V8_TARGET_ARCH_ARM 11 #include "src/compiler/arm/instruction-codes-arm.h" 12 #elif V8_TARGET_ARCH_ARM64 13 #include "src/compiler/arm64/instruction-codes-arm64.h" 14 #elif V8_TARGET_ARCH_IA32 15 #include "src/compiler/ia32/instruction-codes-ia32.h" 16 #elif V8_TARGET_ARCH_MIPS 17 #include "src/compiler/mips/instruction-codes-mips.h" 18 #elif V8_TARGET_ARCH_MIPS64 19 #include "src/compiler/mips64/instruction-codes-mips64.h" 20 #elif V8_TARGET_ARCH_X64 21 #include "src/compiler/x64/instruction-codes-x64.h" 22 #elif V8_TARGET_ARCH_PPC 23 #include "src/compiler/ppc/instruction-codes-ppc.h" 24 #elif V8_TARGET_ARCH_X87 25 #include "src/compiler/x87/instruction-codes-x87.h" 26 #else 27 #define TARGET_ARCH_OPCODE_LIST(V) 28 #define TARGET_ADDRESSING_MODE_LIST(V) 29 #endif 30 #include "src/utils.h" 31 32 namespace v8 { 33 namespace internal { 34 namespace compiler { 35 36 // Modes for ArchStoreWithWriteBarrier below. 37 enum class RecordWriteMode { kValueIsMap, kValueIsPointer, kValueIsAny }; 38 39 40 // Target-specific opcodes that specify which assembly sequence to emit. 41 // Most opcodes specify a single instruction. 42 #define COMMON_ARCH_OPCODE_LIST(V) \ 43 V(ArchCallCodeObject) \ 44 V(ArchTailCallCodeObject) \ 45 V(ArchCallJSFunction) \ 46 V(ArchTailCallJSFunction) \ 47 V(ArchPrepareCallCFunction) \ 48 V(ArchCallCFunction) \ 49 V(ArchPrepareTailCall) \ 50 V(ArchLazyBailout) \ 51 V(ArchJmp) \ 52 V(ArchLookupSwitch) \ 53 V(ArchTableSwitch) \ 54 V(ArchNop) \ 55 V(ArchThrowTerminator) \ 56 V(ArchDeoptimize) \ 57 V(ArchRet) \ 58 V(ArchStackPointer) \ 59 V(ArchFramePointer) \ 60 V(ArchTruncateDoubleToI) \ 61 V(ArchStoreWithWriteBarrier) \ 62 V(CheckedLoadInt8) \ 63 V(CheckedLoadUint8) \ 64 V(CheckedLoadInt16) \ 65 V(CheckedLoadUint16) \ 66 V(CheckedLoadWord32) \ 67 V(CheckedLoadWord64) \ 68 V(CheckedLoadFloat32) \ 69 V(CheckedLoadFloat64) \ 70 V(CheckedStoreWord8) \ 71 V(CheckedStoreWord16) \ 72 V(CheckedStoreWord32) \ 73 V(CheckedStoreWord64) \ 74 V(CheckedStoreFloat32) \ 75 V(CheckedStoreFloat64) 76 77 #define ARCH_OPCODE_LIST(V) \ 78 COMMON_ARCH_OPCODE_LIST(V) \ 79 TARGET_ARCH_OPCODE_LIST(V) 80 81 enum ArchOpcode { 82 #define DECLARE_ARCH_OPCODE(Name) k##Name, 83 ARCH_OPCODE_LIST(DECLARE_ARCH_OPCODE) 84 #undef DECLARE_ARCH_OPCODE 85 #define COUNT_ARCH_OPCODE(Name) +1 86 kLastArchOpcode = -1 ARCH_OPCODE_LIST(COUNT_ARCH_OPCODE) 87 #undef COUNT_ARCH_OPCODE 88 }; 89 90 std::ostream& operator<<(std::ostream& os, const ArchOpcode& ao); 91 92 // Addressing modes represent the "shape" of inputs to an instruction. 93 // Many instructions support multiple addressing modes. Addressing modes 94 // are encoded into the InstructionCode of the instruction and tell the 95 // code generator after register allocation which assembler method to call. 96 #define ADDRESSING_MODE_LIST(V) \ 97 V(None) \ 98 TARGET_ADDRESSING_MODE_LIST(V) 99 100 enum AddressingMode { 101 #define DECLARE_ADDRESSING_MODE(Name) kMode_##Name, 102 ADDRESSING_MODE_LIST(DECLARE_ADDRESSING_MODE) 103 #undef DECLARE_ADDRESSING_MODE 104 #define COUNT_ADDRESSING_MODE(Name) +1 105 kLastAddressingMode = -1 ADDRESSING_MODE_LIST(COUNT_ADDRESSING_MODE) 106 #undef COUNT_ADDRESSING_MODE 107 }; 108 109 std::ostream& operator<<(std::ostream& os, const AddressingMode& am); 110 111 // The mode of the flags continuation (see below). 112 enum FlagsMode { kFlags_none = 0, kFlags_branch = 1, kFlags_set = 2 }; 113 114 std::ostream& operator<<(std::ostream& os, const FlagsMode& fm); 115 116 // The condition of flags continuation (see below). 117 enum FlagsCondition { 118 kEqual, 119 kNotEqual, 120 kSignedLessThan, 121 kSignedGreaterThanOrEqual, 122 kSignedLessThanOrEqual, 123 kSignedGreaterThan, 124 kUnsignedLessThan, 125 kUnsignedGreaterThanOrEqual, 126 kUnsignedLessThanOrEqual, 127 kUnsignedGreaterThan, 128 kFloatLessThanOrUnordered, 129 kFloatGreaterThanOrEqual, 130 kFloatLessThanOrEqual, 131 kFloatGreaterThanOrUnordered, 132 kFloatLessThan, 133 kFloatGreaterThanOrEqualOrUnordered, 134 kFloatLessThanOrEqualOrUnordered, 135 kFloatGreaterThan, 136 kUnorderedEqual, 137 kUnorderedNotEqual, 138 kOverflow, 139 kNotOverflow 140 }; 141 142 inline FlagsCondition NegateFlagsCondition(FlagsCondition condition) { 143 return static_cast<FlagsCondition>(condition ^ 1); 144 } 145 146 FlagsCondition CommuteFlagsCondition(FlagsCondition condition); 147 148 std::ostream& operator<<(std::ostream& os, const FlagsCondition& fc); 149 150 // The InstructionCode is an opaque, target-specific integer that encodes 151 // what code to emit for an instruction in the code generator. It is not 152 // interesting to the register allocator, as the inputs and flags on the 153 // instructions specify everything of interest. 154 typedef int32_t InstructionCode; 155 156 // Helpers for encoding / decoding InstructionCode into the fields needed 157 // for code generation. We encode the instruction, addressing mode, and flags 158 // continuation into a single InstructionCode which is stored as part of 159 // the instruction. 160 typedef BitField<ArchOpcode, 0, 8> ArchOpcodeField; 161 typedef BitField<AddressingMode, 8, 5> AddressingModeField; 162 typedef BitField<FlagsMode, 13, 2> FlagsModeField; 163 typedef BitField<FlagsCondition, 15, 5> FlagsConditionField; 164 typedef BitField<int, 20, 12> MiscField; 165 166 } // namespace compiler 167 } // namespace internal 168 } // namespace v8 169 170 #endif // V8_COMPILER_INSTRUCTION_CODES_H_ 171
