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    Searched defs:Cycles (Results 1 - 6 of 6) sorted by null

  /external/llvm/lib/Target/X86/
X86PadShortFunction.cpp 42 // Cycles - Number of cycles until return if HasReturn is true, otherwise
43 // number of cycles until end of the BB
44 unsigned int Cycles;
46 VisitedBBInfo() : HasReturn(false), Cycles(0) {}
47 VisitedBBInfo(bool HasReturn, unsigned int Cycles)
48 : HasReturn(HasReturn), Cycles(Cycles) {}
64 unsigned int Cycles = 0);
67 unsigned int &Cycles);
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  /external/dagger2/compiler/src/it/functional-tests/src/main/java/test/cycle/
Cycles.java 39 final class Cycles {
40 private Cycles() {}
  /external/llvm/include/llvm/CodeGen/
MachineTraceMetrics.h 36 // cycles required to execute the trace when execution is limited by data
38 // of cycles required to execute all instructions in the trace when ignoring
41 // Every instruction in the current block has a slack - the number of cycles
110 /// Get the scaled number of cycles used per processor resource in MBB.
206 /// Critical path length. This is the number of cycles in the longest data
228 /// Minimum number of cycles from this instruction is issued to the of the
252 /// This is the number of cycles required to execute all instructions from
258 /// Return the resource length of the trace. This is the number of cycles
279 return TE.Cycles.lookup(MI);
282 /// Return the slack of MI. This is the number of cycles MI can be delaye
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  /external/llvm/include/llvm/MC/
MCSchedule.h 41 // fixed number of cycles after dispatch. If a resource is unbuffered, then
54 /// scheduling class for the specified number of cycles.
57 unsigned Cycles;
60 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
64 /// Specify the latency in cpu cycles for a particular scheduling class and def
70 int Cycles;
74 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
78 /// Specify the number of cycles allowed after instruction issue before
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  /external/llvm/lib/Target/AMDGPU/
R600InstrInfo.cpp 418 unsigned Cycles[3] = { 2, 1, 0};
419 return Cycles[Op];
422 unsigned Cycles[3] = { 1, 2, 2};
423 return Cycles[Op];
426 unsigned Cycles[3] = { 2, 1, 2};
427 return Cycles[Op];
430 unsigned Cycles[3] = { 2, 2, 1};
431 return Cycles[Op];
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  /external/llvm/utils/TableGen/
SubtargetEmitter.cpp 92 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
288 // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
289 int Cycles = Stage->getValueAsInt("Cycles");
290 ItinString += " { " + itostr(Cycles) + ", ";
317 // number of operands that has cycles specified.
418 // operand cycles, and pipepine bypess tables. Then add the new Itinerary
469 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
517 // Closing operand cycles
518 OperandCycleTable += " 0 // End operand cycles\n"
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