1 // Copyright 2011 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_ARM_CONSTANTS_ARM_H_ 6 #define V8_ARM_CONSTANTS_ARM_H_ 7 8 #include <stdint.h> 9 10 #include "src/base/logging.h" 11 #include "src/base/macros.h" 12 #include "src/globals.h" 13 14 // ARM EABI is required. 15 #if defined(__arm__) && !defined(__ARM_EABI__) 16 #error ARM EABI support is required. 17 #endif 18 19 namespace v8 { 20 namespace internal { 21 22 // Constant pool marker. 23 // Use UDF, the permanently undefined instruction. 24 const int kConstantPoolMarkerMask = 0xfff000f0; 25 const int kConstantPoolMarker = 0xe7f000f0; 26 const int kConstantPoolLengthMaxMask = 0xffff; 27 inline int EncodeConstantPoolLength(int length) { 28 DCHECK((length & kConstantPoolLengthMaxMask) == length); 29 return ((length & 0xfff0) << 4) | (length & 0xf); 30 } 31 inline int DecodeConstantPoolLength(int instr) { 32 DCHECK((instr & kConstantPoolMarkerMask) == kConstantPoolMarker); 33 return ((instr >> 4) & 0xfff0) | (instr & 0xf); 34 } 35 36 // Used in code age prologue - ldr(pc, MemOperand(pc, -4)) 37 const int kCodeAgeJumpInstruction = 0xe51ff004; 38 39 // Number of registers in normal ARM mode. 40 const int kNumRegisters = 16; 41 42 // VFP support. 43 const int kNumVFPSingleRegisters = 32; 44 const int kNumVFPDoubleRegisters = 32; 45 const int kNumVFPRegisters = kNumVFPSingleRegisters + kNumVFPDoubleRegisters; 46 47 // PC is register 15. 48 const int kPCRegister = 15; 49 const int kNoRegister = -1; 50 51 // Used in embedded constant pool builder - max reach in bits for 52 // various load instructions (unsigned) 53 const int kLdrMaxReachBits = 12; 54 const int kVldrMaxReachBits = 10; 55 56 // ----------------------------------------------------------------------------- 57 // Conditions. 58 59 // Defines constants and accessor classes to assemble, disassemble and 60 // simulate ARM instructions. 61 // 62 // Section references in the code refer to the "ARM Architecture Reference 63 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf) 64 // 65 // Constants for specific fields are defined in their respective named enums. 66 // General constants are in an anonymous enum in class Instr. 67 68 // Values for the condition field as defined in section A3.2 69 enum Condition { 70 kNoCondition = -1, 71 72 eq = 0 << 28, // Z set Equal. 73 ne = 1 << 28, // Z clear Not equal. 74 cs = 2 << 28, // C set Unsigned higher or same. 75 cc = 3 << 28, // C clear Unsigned lower. 76 mi = 4 << 28, // N set Negative. 77 pl = 5 << 28, // N clear Positive or zero. 78 vs = 6 << 28, // V set Overflow. 79 vc = 7 << 28, // V clear No overflow. 80 hi = 8 << 28, // C set, Z clear Unsigned higher. 81 ls = 9 << 28, // C clear or Z set Unsigned lower or same. 82 ge = 10 << 28, // N == V Greater or equal. 83 lt = 11 << 28, // N != V Less than. 84 gt = 12 << 28, // Z clear, N == V Greater than. 85 le = 13 << 28, // Z set or N != V Less then or equal 86 al = 14 << 28, // Always. 87 88 kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1). 89 kNumberOfConditions = 16, 90 91 // Aliases. 92 hs = cs, // C set Unsigned higher or same. 93 lo = cc // C clear Unsigned lower. 94 }; 95 96 97 inline Condition NegateCondition(Condition cond) { 98 DCHECK(cond != al); 99 return static_cast<Condition>(cond ^ ne); 100 } 101 102 103 // Commute a condition such that {a cond b == b cond' a}. 104 inline Condition CommuteCondition(Condition cond) { 105 switch (cond) { 106 case lo: 107 return hi; 108 case hi: 109 return lo; 110 case hs: 111 return ls; 112 case ls: 113 return hs; 114 case lt: 115 return gt; 116 case gt: 117 return lt; 118 case ge: 119 return le; 120 case le: 121 return ge; 122 default: 123 return cond; 124 } 125 } 126 127 128 // ----------------------------------------------------------------------------- 129 // Instructions encoding. 130 131 // Instr is merely used by the Assembler to distinguish 32bit integers 132 // representing instructions from usual 32 bit values. 133 // Instruction objects are pointers to 32bit values, and provide methods to 134 // access the various ISA fields. 135 typedef int32_t Instr; 136 137 138 // Opcodes for Data-processing instructions (instructions with a type 0 and 1) 139 // as defined in section A3.4 140 enum Opcode { 141 AND = 0 << 21, // Logical AND. 142 EOR = 1 << 21, // Logical Exclusive OR. 143 SUB = 2 << 21, // Subtract. 144 RSB = 3 << 21, // Reverse Subtract. 145 ADD = 4 << 21, // Add. 146 ADC = 5 << 21, // Add with Carry. 147 SBC = 6 << 21, // Subtract with Carry. 148 RSC = 7 << 21, // Reverse Subtract with Carry. 149 TST = 8 << 21, // Test. 150 TEQ = 9 << 21, // Test Equivalence. 151 CMP = 10 << 21, // Compare. 152 CMN = 11 << 21, // Compare Negated. 153 ORR = 12 << 21, // Logical (inclusive) OR. 154 MOV = 13 << 21, // Move. 155 BIC = 14 << 21, // Bit Clear. 156 MVN = 15 << 21 // Move Not. 157 }; 158 159 160 // The bits for bit 7-4 for some type 0 miscellaneous instructions. 161 enum MiscInstructionsBits74 { 162 // With bits 22-21 01. 163 BX = 1 << 4, 164 BXJ = 2 << 4, 165 BLX = 3 << 4, 166 BKPT = 7 << 4, 167 168 // With bits 22-21 11. 169 CLZ = 1 << 4 170 }; 171 172 173 // Instruction encoding bits and masks. 174 enum { 175 H = 1 << 5, // Halfword (or byte). 176 S6 = 1 << 6, // Signed (or unsigned). 177 L = 1 << 20, // Load (or store). 178 S = 1 << 20, // Set condition code (or leave unchanged). 179 W = 1 << 21, // Writeback base register (or leave unchanged). 180 A = 1 << 21, // Accumulate in multiply instruction (or not). 181 B = 1 << 22, // Unsigned byte (or word). 182 N = 1 << 22, // Long (or short). 183 U = 1 << 23, // Positive (or negative) offset/index. 184 P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing). 185 I = 1 << 25, // Immediate shifter operand (or not). 186 B0 = 1 << 0, 187 B4 = 1 << 4, 188 B5 = 1 << 5, 189 B6 = 1 << 6, 190 B7 = 1 << 7, 191 B8 = 1 << 8, 192 B9 = 1 << 9, 193 B12 = 1 << 12, 194 B16 = 1 << 16, 195 B17 = 1 << 17, 196 B18 = 1 << 18, 197 B19 = 1 << 19, 198 B20 = 1 << 20, 199 B21 = 1 << 21, 200 B22 = 1 << 22, 201 B23 = 1 << 23, 202 B24 = 1 << 24, 203 B25 = 1 << 25, 204 B26 = 1 << 26, 205 B27 = 1 << 27, 206 B28 = 1 << 28, 207 208 // Instruction bit masks. 209 kCondMask = 15 << 28, 210 kALUMask = 0x6f << 21, 211 kRdMask = 15 << 12, // In str instruction. 212 kCoprocessorMask = 15 << 8, 213 kOpCodeMask = 15 << 21, // In data-processing instructions. 214 kImm24Mask = (1 << 24) - 1, 215 kImm16Mask = (1 << 16) - 1, 216 kImm8Mask = (1 << 8) - 1, 217 kOff12Mask = (1 << 12) - 1, 218 kOff8Mask = (1 << 8) - 1 219 }; 220 221 222 // ----------------------------------------------------------------------------- 223 // Addressing modes and instruction variants. 224 225 // Condition code updating mode. 226 enum SBit { 227 SetCC = 1 << 20, // Set condition code. 228 LeaveCC = 0 << 20 // Leave condition code unchanged. 229 }; 230 231 232 // Status register selection. 233 enum SRegister { 234 CPSR = 0 << 22, 235 SPSR = 1 << 22 236 }; 237 238 239 // Shifter types for Data-processing operands as defined in section A5.1.2. 240 enum ShiftOp { 241 LSL = 0 << 5, // Logical shift left. 242 LSR = 1 << 5, // Logical shift right. 243 ASR = 2 << 5, // Arithmetic shift right. 244 ROR = 3 << 5, // Rotate right. 245 246 // RRX is encoded as ROR with shift_imm == 0. 247 // Use a special code to make the distinction. The RRX ShiftOp is only used 248 // as an argument, and will never actually be encoded. The Assembler will 249 // detect it and emit the correct ROR shift operand with shift_imm == 0. 250 RRX = -1, 251 kNumberOfShifts = 4 252 }; 253 254 255 // Status register fields. 256 enum SRegisterField { 257 CPSR_c = CPSR | 1 << 16, 258 CPSR_x = CPSR | 1 << 17, 259 CPSR_s = CPSR | 1 << 18, 260 CPSR_f = CPSR | 1 << 19, 261 SPSR_c = SPSR | 1 << 16, 262 SPSR_x = SPSR | 1 << 17, 263 SPSR_s = SPSR | 1 << 18, 264 SPSR_f = SPSR | 1 << 19 265 }; 266 267 // Status register field mask (or'ed SRegisterField enum values). 268 typedef uint32_t SRegisterFieldMask; 269 270 271 // Memory operand addressing mode. 272 enum AddrMode { 273 // Bit encoding P U W. 274 Offset = (8|4|0) << 21, // Offset (without writeback to base). 275 PreIndex = (8|4|1) << 21, // Pre-indexed addressing with writeback. 276 PostIndex = (0|4|0) << 21, // Post-indexed addressing with writeback. 277 NegOffset = (8|0|0) << 21, // Negative offset (without writeback to base). 278 NegPreIndex = (8|0|1) << 21, // Negative pre-indexed with writeback. 279 NegPostIndex = (0|0|0) << 21 // Negative post-indexed with writeback. 280 }; 281 282 283 // Load/store multiple addressing mode. 284 enum BlockAddrMode { 285 // Bit encoding P U W . 286 da = (0|0|0) << 21, // Decrement after. 287 ia = (0|4|0) << 21, // Increment after. 288 db = (8|0|0) << 21, // Decrement before. 289 ib = (8|4|0) << 21, // Increment before. 290 da_w = (0|0|1) << 21, // Decrement after with writeback to base. 291 ia_w = (0|4|1) << 21, // Increment after with writeback to base. 292 db_w = (8|0|1) << 21, // Decrement before with writeback to base. 293 ib_w = (8|4|1) << 21, // Increment before with writeback to base. 294 295 // Alias modes for comparison when writeback does not matter. 296 da_x = (0|0|0) << 21, // Decrement after. 297 ia_x = (0|4|0) << 21, // Increment after. 298 db_x = (8|0|0) << 21, // Decrement before. 299 ib_x = (8|4|0) << 21, // Increment before. 300 301 kBlockAddrModeMask = (8|4|1) << 21 302 }; 303 304 305 // Coprocessor load/store operand size. 306 enum LFlag { 307 Long = 1 << 22, // Long load/store coprocessor. 308 Short = 0 << 22 // Short load/store coprocessor. 309 }; 310 311 312 // NEON data type 313 enum NeonDataType { 314 NeonS8 = 0x1, // U = 0, imm3 = 0b001 315 NeonS16 = 0x2, // U = 0, imm3 = 0b010 316 NeonS32 = 0x4, // U = 0, imm3 = 0b100 317 NeonU8 = 1 << 24 | 0x1, // U = 1, imm3 = 0b001 318 NeonU16 = 1 << 24 | 0x2, // U = 1, imm3 = 0b010 319 NeonU32 = 1 << 24 | 0x4, // U = 1, imm3 = 0b100 320 NeonDataTypeSizeMask = 0x7, 321 NeonDataTypeUMask = 1 << 24 322 }; 323 324 enum NeonListType { 325 nlt_1 = 0x7, 326 nlt_2 = 0xA, 327 nlt_3 = 0x6, 328 nlt_4 = 0x2 329 }; 330 331 enum NeonSize { 332 Neon8 = 0x0, 333 Neon16 = 0x1, 334 Neon32 = 0x2, 335 Neon64 = 0x3 336 }; 337 338 // ----------------------------------------------------------------------------- 339 // Supervisor Call (svc) specific support. 340 341 // Special Software Interrupt codes when used in the presence of the ARM 342 // simulator. 343 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for 344 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature. 345 enum SoftwareInterruptCodes { 346 // transition to C code 347 kCallRtRedirected = 0x10, 348 // break point 349 kBreakpoint = 0x20, 350 // stop 351 kStopCode = 1 << 23 352 }; 353 const uint32_t kStopCodeMask = kStopCode - 1; 354 const uint32_t kMaxStopCode = kStopCode - 1; 355 const int32_t kDefaultStopCode = -1; 356 357 358 // Type of VFP register. Determines register encoding. 359 enum VFPRegPrecision { 360 kSinglePrecision = 0, 361 kDoublePrecision = 1 362 }; 363 364 365 // VFP FPSCR constants. 366 enum VFPConversionMode { 367 kFPSCRRounding = 0, 368 kDefaultRoundToZero = 1 369 }; 370 371 // This mask does not include the "inexact" or "input denormal" cumulative 372 // exceptions flags, because we usually don't want to check for it. 373 const uint32_t kVFPExceptionMask = 0xf; 374 const uint32_t kVFPInvalidOpExceptionBit = 1 << 0; 375 const uint32_t kVFPOverflowExceptionBit = 1 << 2; 376 const uint32_t kVFPUnderflowExceptionBit = 1 << 3; 377 const uint32_t kVFPInexactExceptionBit = 1 << 4; 378 const uint32_t kVFPFlushToZeroMask = 1 << 24; 379 const uint32_t kVFPDefaultNaNModeControlBit = 1 << 25; 380 381 const uint32_t kVFPNConditionFlagBit = 1 << 31; 382 const uint32_t kVFPZConditionFlagBit = 1 << 30; 383 const uint32_t kVFPCConditionFlagBit = 1 << 29; 384 const uint32_t kVFPVConditionFlagBit = 1 << 28; 385 386 387 // VFP rounding modes. See ARM DDI 0406B Page A2-29. 388 enum VFPRoundingMode { 389 RN = 0 << 22, // Round to Nearest. 390 RP = 1 << 22, // Round towards Plus Infinity. 391 RM = 2 << 22, // Round towards Minus Infinity. 392 RZ = 3 << 22, // Round towards zero. 393 394 // Aliases. 395 kRoundToNearest = RN, 396 kRoundToPlusInf = RP, 397 kRoundToMinusInf = RM, 398 kRoundToZero = RZ 399 }; 400 401 const uint32_t kVFPRoundingModeMask = 3 << 22; 402 403 enum CheckForInexactConversion { 404 kCheckForInexactConversion, 405 kDontCheckForInexactConversion 406 }; 407 408 // ----------------------------------------------------------------------------- 409 // Hints. 410 411 // Branch hints are not used on the ARM. They are defined so that they can 412 // appear in shared function signatures, but will be ignored in ARM 413 // implementations. 414 enum Hint { no_hint }; 415 416 // Hints are not used on the arm. Negating is trivial. 417 inline Hint NegateHint(Hint ignored) { return no_hint; } 418 419 420 // ----------------------------------------------------------------------------- 421 // Instruction abstraction. 422 423 // The class Instruction enables access to individual fields defined in the ARM 424 // architecture instruction set encoding as described in figure A3-1. 425 // Note that the Assembler uses typedef int32_t Instr. 426 // 427 // Example: Test whether the instruction at ptr does set the condition code 428 // bits. 429 // 430 // bool InstructionSetsConditionCodes(byte* ptr) { 431 // Instruction* instr = Instruction::At(ptr); 432 // int type = instr->TypeValue(); 433 // return ((type == 0) || (type == 1)) && instr->HasS(); 434 // } 435 // 436 class Instruction { 437 public: 438 enum { 439 kInstrSize = 4, 440 kInstrSizeLog2 = 2, 441 kPCReadOffset = 8 442 }; 443 444 // Helper macro to define static accessors. 445 // We use the cast to char* trick to bypass the strict anti-aliasing rules. 446 #define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \ 447 static inline return_type Name(Instr instr) { \ 448 char* temp = reinterpret_cast<char*>(&instr); \ 449 return reinterpret_cast<Instruction*>(temp)->Name(); \ 450 } 451 452 #define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name) 453 454 // Get the raw instruction bits. 455 inline Instr InstructionBits() const { 456 return *reinterpret_cast<const Instr*>(this); 457 } 458 459 // Set the raw instruction bits to value. 460 inline void SetInstructionBits(Instr value) { 461 *reinterpret_cast<Instr*>(this) = value; 462 } 463 464 // Read one particular bit out of the instruction bits. 465 inline int Bit(int nr) const { 466 return (InstructionBits() >> nr) & 1; 467 } 468 469 // Read a bit field's value out of the instruction bits. 470 inline int Bits(int hi, int lo) const { 471 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); 472 } 473 474 // Read a bit field out of the instruction bits. 475 inline int BitField(int hi, int lo) const { 476 return InstructionBits() & (((2 << (hi - lo)) - 1) << lo); 477 } 478 479 // Static support. 480 481 // Read one particular bit out of the instruction bits. 482 static inline int Bit(Instr instr, int nr) { 483 return (instr >> nr) & 1; 484 } 485 486 // Read the value of a bit field out of the instruction bits. 487 static inline int Bits(Instr instr, int hi, int lo) { 488 return (instr >> lo) & ((2 << (hi - lo)) - 1); 489 } 490 491 492 // Read a bit field out of the instruction bits. 493 static inline int BitField(Instr instr, int hi, int lo) { 494 return instr & (((2 << (hi - lo)) - 1) << lo); 495 } 496 497 498 // Accessors for the different named fields used in the ARM encoding. 499 // The naming of these accessor corresponds to figure A3-1. 500 // 501 // Two kind of accessors are declared: 502 // - <Name>Field() will return the raw field, i.e. the field's bits at their 503 // original place in the instruction encoding. 504 // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as 505 // 0xC0810002 ConditionField(instr) will return 0xC0000000. 506 // - <Name>Value() will return the field value, shifted back to bit 0. 507 // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as 508 // 0xC0810002 ConditionField(instr) will return 0xC. 509 510 511 // Generally applicable fields 512 inline Condition ConditionValue() const { 513 return static_cast<Condition>(Bits(31, 28)); 514 } 515 inline Condition ConditionField() const { 516 return static_cast<Condition>(BitField(31, 28)); 517 } 518 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionValue); 519 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField); 520 521 inline int TypeValue() const { return Bits(27, 25); } 522 inline int SpecialValue() const { return Bits(27, 23); } 523 524 inline int RnValue() const { return Bits(19, 16); } 525 DECLARE_STATIC_ACCESSOR(RnValue); 526 inline int RdValue() const { return Bits(15, 12); } 527 DECLARE_STATIC_ACCESSOR(RdValue); 528 529 inline int CoprocessorValue() const { return Bits(11, 8); } 530 // Support for VFP. 531 // Vn(19-16) | Vd(15-12) | Vm(3-0) 532 inline int VnValue() const { return Bits(19, 16); } 533 inline int VmValue() const { return Bits(3, 0); } 534 inline int VdValue() const { return Bits(15, 12); } 535 inline int NValue() const { return Bit(7); } 536 inline int MValue() const { return Bit(5); } 537 inline int DValue() const { return Bit(22); } 538 inline int RtValue() const { return Bits(15, 12); } 539 inline int PValue() const { return Bit(24); } 540 inline int UValue() const { return Bit(23); } 541 inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); } 542 inline int Opc2Value() const { return Bits(19, 16); } 543 inline int Opc3Value() const { return Bits(7, 6); } 544 inline int SzValue() const { return Bit(8); } 545 inline int VLValue() const { return Bit(20); } 546 inline int VCValue() const { return Bit(8); } 547 inline int VAValue() const { return Bits(23, 21); } 548 inline int VBValue() const { return Bits(6, 5); } 549 inline int VFPNRegValue(VFPRegPrecision pre) { 550 return VFPGlueRegValue(pre, 16, 7); 551 } 552 inline int VFPMRegValue(VFPRegPrecision pre) { 553 return VFPGlueRegValue(pre, 0, 5); 554 } 555 inline int VFPDRegValue(VFPRegPrecision pre) { 556 return VFPGlueRegValue(pre, 12, 22); 557 } 558 559 // Fields used in Data processing instructions 560 inline int OpcodeValue() const { 561 return static_cast<Opcode>(Bits(24, 21)); 562 } 563 inline Opcode OpcodeField() const { 564 return static_cast<Opcode>(BitField(24, 21)); 565 } 566 inline int SValue() const { return Bit(20); } 567 // with register 568 inline int RmValue() const { return Bits(3, 0); } 569 DECLARE_STATIC_ACCESSOR(RmValue); 570 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); } 571 inline ShiftOp ShiftField() const { 572 return static_cast<ShiftOp>(BitField(6, 5)); 573 } 574 inline int RegShiftValue() const { return Bit(4); } 575 inline int RsValue() const { return Bits(11, 8); } 576 inline int ShiftAmountValue() const { return Bits(11, 7); } 577 // with immediate 578 inline int RotateValue() const { return Bits(11, 8); } 579 DECLARE_STATIC_ACCESSOR(RotateValue); 580 inline int Immed8Value() const { return Bits(7, 0); } 581 DECLARE_STATIC_ACCESSOR(Immed8Value); 582 inline int Immed4Value() const { return Bits(19, 16); } 583 inline int ImmedMovwMovtValue() const { 584 return Immed4Value() << 12 | Offset12Value(); } 585 DECLARE_STATIC_ACCESSOR(ImmedMovwMovtValue); 586 587 // Fields used in Load/Store instructions 588 inline int PUValue() const { return Bits(24, 23); } 589 inline int PUField() const { return BitField(24, 23); } 590 inline int BValue() const { return Bit(22); } 591 inline int WValue() const { return Bit(21); } 592 inline int LValue() const { return Bit(20); } 593 // with register uses same fields as Data processing instructions above 594 // with immediate 595 inline int Offset12Value() const { return Bits(11, 0); } 596 // multiple 597 inline int RlistValue() const { return Bits(15, 0); } 598 // extra loads and stores 599 inline int SignValue() const { return Bit(6); } 600 inline int HValue() const { return Bit(5); } 601 inline int ImmedHValue() const { return Bits(11, 8); } 602 inline int ImmedLValue() const { return Bits(3, 0); } 603 604 // Fields used in Branch instructions 605 inline int LinkValue() const { return Bit(24); } 606 inline int SImmed24Value() const { return ((InstructionBits() << 8) >> 8); } 607 608 // Fields used in Software interrupt instructions 609 inline SoftwareInterruptCodes SvcValue() const { 610 return static_cast<SoftwareInterruptCodes>(Bits(23, 0)); 611 } 612 613 // Test for special encodings of type 0 instructions (extra loads and stores, 614 // as well as multiplications). 615 inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); } 616 617 // Test for miscellaneous instructions encodings of type 0 instructions. 618 inline bool IsMiscType0() const { return (Bit(24) == 1) 619 && (Bit(23) == 0) 620 && (Bit(20) == 0) 621 && ((Bit(7) == 0)); } 622 623 // Test for a nop instruction, which falls under type 1. 624 inline bool IsNopType1() const { return Bits(24, 0) == 0x0120F000; } 625 626 // Test for a stop instruction. 627 inline bool IsStop() const { 628 return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode); 629 } 630 631 // Special accessors that test for existence of a value. 632 inline bool HasS() const { return SValue() == 1; } 633 inline bool HasB() const { return BValue() == 1; } 634 inline bool HasW() const { return WValue() == 1; } 635 inline bool HasL() const { return LValue() == 1; } 636 inline bool HasU() const { return UValue() == 1; } 637 inline bool HasSign() const { return SignValue() == 1; } 638 inline bool HasH() const { return HValue() == 1; } 639 inline bool HasLink() const { return LinkValue() == 1; } 640 641 // Decoding the double immediate in the vmov instruction. 642 double DoubleImmedVmov() const; 643 644 // Instructions are read of out a code stream. The only way to get a 645 // reference to an instruction is to convert a pointer. There is no way 646 // to allocate or create instances of class Instruction. 647 // Use the At(pc) function to create references to Instruction. 648 static Instruction* At(byte* pc) { 649 return reinterpret_cast<Instruction*>(pc); 650 } 651 652 653 private: 654 // Join split register codes, depending on single or double precision. 655 // four_bit is the position of the least-significant bit of the four 656 // bit specifier. one_bit is the position of the additional single bit 657 // specifier. 658 inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) { 659 if (pre == kSinglePrecision) { 660 return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit); 661 } 662 return (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit); 663 } 664 665 // We need to prevent the creation of instances of class Instruction. 666 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); 667 }; 668 669 670 // Helper functions for converting between register numbers and names. 671 class Registers { 672 public: 673 // Return the name of the register. 674 static const char* Name(int reg); 675 676 // Lookup the register number for the name provided. 677 static int Number(const char* name); 678 679 struct RegisterAlias { 680 int reg; 681 const char* name; 682 }; 683 684 private: 685 static const char* names_[kNumRegisters]; 686 static const RegisterAlias aliases_[]; 687 }; 688 689 // Helper functions for converting between VFP register numbers and names. 690 class VFPRegisters { 691 public: 692 // Return the name of the register. 693 static const char* Name(int reg, bool is_double); 694 695 // Lookup the register number for the name provided. 696 // Set flag pointed by is_double to true if register 697 // is double-precision. 698 static int Number(const char* name, bool* is_double); 699 700 private: 701 static const char* names_[kNumVFPRegisters]; 702 }; 703 704 705 } // namespace internal 706 } // namespace v8 707 708 #endif // V8_ARM_CONSTANTS_ARM_H_ 709
