| /external/llvm/lib/CodeGen/ |
| PHIEliminationUtils.cpp | 36 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo();
37 for (MachineInstr &RI : MRI.reg_instructions(SrcReg)) {
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| CriticalAntiDepBreaker.h | 36 MachineRegisterInfo &MRI;
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| DeadMachineInstructionElim.cpp | 35 const MachineRegisterInfo *MRI;
78 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
81 if (!MRI->use_nodbg_empty(Reg))
97 MRI = &MF.getRegInfo();
106 LivePhysRegs = MRI->getReservedRegs();
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| RegAllocBase.h | 62 MachineRegisterInfo *MRI;
69 : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
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| TargetFrameLoweringImpl.cpp | 78 const MachineRegisterInfo &MRI = MF.getRegInfo();
81 if (CallsUnwindInit || MRI.isPhysRegModified(Reg))
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| ProcessImplicitDefs.cpp | 31 MachineRegisterInfo *MRI;
84 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
144 MRI = &MF.getRegInfo();
145 assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
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| AggressiveAntiDepBreaker.h | 114 MachineRegisterInfo &MRI;
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| LiveRangeCalc.h | 38 const MachineRegisterInfo *MRI;
138 LiveRangeCalc() : MF(nullptr), MRI(nullptr), Indexes(nullptr),
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| OptimizePHIs.cpp | 33 MachineRegisterInfo *MRI;
69 MRI = &Fn.getRegInfo();
107 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
114 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
147 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) {
171 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
174 MRI->replaceRegWith(OldReg, SingleValReg);
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| UnreachableBlockElim.cpp | 193 MachineRegisterInfo &MRI = F.getRegInfo();
194 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
195 MRI.replaceRegWith(Output, Input);
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAsmBackendDarwin.h | 19 const MCRegisterInfo &MRI;
23 const MCRegisterInfo &MRI, MachO::CPUSubTypeARM st)
24 : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), MRI(MRI), Subtype(st) {
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| /external/llvm/include/llvm/CodeGen/ |
| MachineSSAUpdater.h | 55 MachineRegisterInfo *MRI;
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| LiveVariables.h | 111 MachineRegisterInfo &MRI);
130 MachineRegisterInfo* MRI;
286 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI);
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| /external/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| WebAssemblyMCCodeEmitter.cpp | 31 const MCRegisterInfo &MRI;
34 WebAssemblyMCCodeEmitter(const MCInstrInfo &, const MCRegisterInfo &mri,
36 : MRI(mri) {}
63 const MCRegisterInfo &MRI,
65 return new WebAssemblyMCCodeEmitter(MCII, MRI, Ctx);
72 return MRI.getEncodingValue(MO.getReg());
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.h | 31 MachineRegisterInfo *MRI;
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| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyInstrInfo.cpp | 41 auto &MRI = MBB.getParent()->getRegInfo();
43 MRI.getRegClass(DestReg) :
44 MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(SrcReg);
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| WebAssemblyLowerBrUnless.cpp | 61 auto &MRI = MF.getRegInfo();
74 assert(MRI.hasOneDef(Cond));
75 MachineInstr *Def = MRI.getVRegDef(Cond);
109 unsigned ZeroReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
113 unsigned Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
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| WebAssemblyPeephole.cpp | 50 MachineRegisterInfo &MRI = MF.getRegInfo();
76 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
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| WebAssemblyRegNumbering.cpp | 63 MachineRegisterInfo &MRI = MF.getRegInfo();
98 if (MRI.use_empty(VReg))
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| WebAssemblyStoreResults.cpp | 72 const MachineRegisterInfo &MRI = MF.getRegInfo();
76 assert(MRI.isSSA() && "StoreResults depends on SSA form");
95 for (auto I = MRI.use_begin(FromReg), E = MRI.use_end(); I != E;) {
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| WebAssemblyRegisterInfo.cpp | 75 auto &MRI = MF.getRegInfo();
78 unsigned OffsetReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterDwarf.cpp | 183 const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo();
184 int Reg = MRI->getDwarfRegNum(MLoc.getReg(), false);
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXPeephole.cpp | 83 const auto &MRI = MF.getRegInfo();
86 GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg());
108 const auto &MRI = MF.getRegInfo();
110 auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
120 // Check if MRI has only one non dbg use, which is Root
121 if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg())) {
144 const auto &MRI = MF.getRegInfo();
145 if (MRI.use_empty(NVPTX::VRFrame)) {
146 if (auto MI = MRI.getUniqueVRegDef(NVPTX::VRFrame)) {
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo();
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]);
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg);
115 AddLiveIn(&MF, MRI, new_reg, virt_reg);
123 MachineRegisterInfo & MRI,
127 if (!MRI.isLiveIn(physReg)) {
128 MRI.addLiveIn(physReg, virtReg);
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg))
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstPrinter.h | 46 const MCRegisterInfo &MRI;
62 const MCRegisterInfo &mri)
63 : CommentStream(nullptr), MAI(mai), MII(mii), MRI(mri), UseMarkup(0),
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