| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 110 unsigned NewReg;
116 NewReg = AArch64::WZR;
119 NewReg = AArch64::XZR;
123 MO.setReg(NewReg);
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyPeephole.cpp | 76 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
77 MO.setReg(NewReg);
79 MFI.stackifyVReg(NewReg);
80 MFI.addWAReg(NewReg, WebAssemblyFunctionInfo::UnusedReg);
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 282 MCOperand NewReg;
287 NewReg = MCOperand::createReg(MRI.getMatchingSuperReg(
289 NewMI.addOperand(NewReg);
[all...] |
| /external/llvm/lib/CodeGen/ |
| CriticalAntiDepBreaker.cpp | 319 // be replaced by NewReg. Return true if any of their parent instructions may
324 // the two-address instruction also defines NewReg, as may happen with
328 // both NewReg and AntiDepReg covers it.
332 unsigned NewReg)
338 // operands, in case they may be assigned to NewReg. In this case antidep
343 // Handle cases in which this instruction defines NewReg.
348 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
352 CheckOper.getReg() != NewReg)
355 // Don't allow the instruction to define NewReg and AntiDepReg.
361 // NewReg
[all...] |
| MachineCSE.cpp | 541 unsigned NewReg = CSMI->getOperand(i).getReg();
550 if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg)
553 if (OldReg == NewReg) {
559 TargetRegisterInfo::isVirtualRegister(NewReg) &&
562 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
571 if (!MRI->constrainRegClass(NewReg, OldRC)) {
577 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
585 unsigned NewReg = CSEPairs[i].second;
587 MachineInstr *Def = MRI->getUniqueVRegDef(NewReg);
589 Def->clearRegisterDeads(NewReg);
[all...] |
| TailDuplication.cpp | 89 void AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
379 void TailDuplicatePass::AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
383 LI->second.push_back(std::make_pair(BB, NewReg));
386 Vals.push_back(std::make_pair(BB, NewReg));
441 unsigned NewReg = MRI->createVirtualRegister(RC);
442 MO.setReg(NewReg);
443 LocalVRMap.insert(std::make_pair(Reg, NewReg));
445 AddSSAUpdateEntry(Reg, NewReg, PredBB);
[all...] |
| PeepholeOptimizer.cpp | 801 /// \brief Rewrite the current source with \p NewReg and \p NewSubReg
804 virtual bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) {
808 MOSrc.setReg(NewReg);
[all...] |
| TwoAddressInstructionPass.cpp | 738 unsigned NewReg = 0;
741 NewReg, IsDstPhys)) {
751 VirtRegPairs.push_back(NewReg);
754 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
756 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
757 VirtRegPairs.push_back(NewReg);
758 Reg = NewReg;
[all...] |
| RegisterCoalescer.cpp | 681 unsigned NewReg = NewDstMO.getReg();
682 if (NewReg != IntB.reg || !IntB.Query(AValNo->def).isKill())
746 UseMO.setReg(NewReg);
756 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
757 UseMO.substPhysReg(NewReg, *TRI);
759 UseMO.setReg(NewReg);
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| ExprEngineCXX.cpp | 491 const MemRegion *NewReg = symVal.castAs<loc::MemRegionVal>().getRegion();
494 getStoreManager().GetElementZeroRegion(NewReg, ObjTy);
|
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 658 unsigned NewReg = optimizeSDPattern(MI);
660 if (NewReg != 0) {
666 // reference into a plain DPR, and that will end poorly. NewReg is
669 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
673 << PrintReg(NewReg) << "\n");
674 (*I)->substVirtReg(NewReg, 0, *TRI);
677 Replacements[MI] = NewReg;
|
| ARMBaseInstrInfo.cpp | [all...] |
| /external/v8/test/unittests/compiler/ |
| instruction-sequence-unittest.h | 185 VReg NewReg() { return VReg(sequence()->NextVirtualRegister()); }
|
| /external/llvm/lib/Target/X86/ |
| X86FloatingPoint.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 586 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
587 Elts.insert(NewReg);
593 NewReg->addSuperClass(Supers[i], Ranges[i]);
600 if (NewReg->getValue(RV.getNameInit()))
624 NewReg->addValue(*Def->getValue(Field));
633 NewReg->addValue(*DefRV);
638 NewReg->addValue(RV);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
