1 /* opcode/i386.h -- Intel 80386 opcode macros 2 Copyright (C) 1989-2014 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived 22 ix86 Unix assemblers, generate floating point instructions with 23 reversed source and destination registers in certain cases. 24 Unfortunately, gcc and possibly many other programs use this 25 reversed syntax, so we're stuck with it. 26 27 eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but 28 `fsub %st,%st(3)' results in st(3) = st - st(3), rather than 29 the expected st(3) = st(3) - st 30 31 This happens with all the non-commutative arithmetic floating point 32 operations with two register operands, where the source register is 33 %st, and destination register is %st(i). 34 35 The affected opcode map is dceX, dcfX, deeX, defX. */ 36 37 #ifndef OPCODE_I386_H 38 #define OPCODE_I386_H 39 40 #ifndef SYSV386_COMPAT 41 /* Set non-zero for broken, compatible instructions. Set to zero for 42 non-broken opcodes at your peril. gcc generates SystemV/386 43 compatible instructions. */ 44 #define SYSV386_COMPAT 1 45 #endif 46 #ifndef OLDGCC_COMPAT 47 /* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could 48 generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands 49 reversed. */ 50 #define OLDGCC_COMPAT SYSV386_COMPAT 51 #endif 52 53 #define MOV_AX_DISP32 0xa0 54 #define POP_SEG_SHORT 0x07 55 #define JUMP_PC_RELATIVE 0xeb 56 #define INT_OPCODE 0xcd 57 #define INT3_OPCODE 0xcc 58 /* The opcode for the fwait instruction, which disassembler treats as a 59 prefix when it can. */ 60 #define FWAIT_OPCODE 0x9b 61 62 /* Instruction prefixes. 63 NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as 64 part of the opcode. Other prefixes may still appear between them 65 and the 0x0f part of the opcode. */ 66 #define ADDR_PREFIX_OPCODE 0x67 67 #define DATA_PREFIX_OPCODE 0x66 68 #define LOCK_PREFIX_OPCODE 0xf0 69 #define CS_PREFIX_OPCODE 0x2e 70 #define DS_PREFIX_OPCODE 0x3e 71 #define ES_PREFIX_OPCODE 0x26 72 #define FS_PREFIX_OPCODE 0x64 73 #define GS_PREFIX_OPCODE 0x65 74 #define SS_PREFIX_OPCODE 0x36 75 #define REPNE_PREFIX_OPCODE 0xf2 76 #define REPE_PREFIX_OPCODE 0xf3 77 #define XACQUIRE_PREFIX_OPCODE 0xf2 78 #define XRELEASE_PREFIX_OPCODE 0xf3 79 #define BND_PREFIX_OPCODE 0xf2 80 81 #define TWO_BYTE_OPCODE_ESCAPE 0x0f 82 #define NOP_OPCODE (char) 0x90 83 84 /* register numbers */ 85 #define EAX_REG_NUM 0 86 #define ECX_REG_NUM 1 87 #define EDX_REG_NUM 2 88 #define EBX_REG_NUM 3 89 #define ESP_REG_NUM 4 90 #define EBP_REG_NUM 5 91 #define ESI_REG_NUM 6 92 #define EDI_REG_NUM 7 93 94 /* modrm_byte.regmem for twobyte escape */ 95 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM 96 /* index_base_byte.index for no index register addressing */ 97 #define NO_INDEX_REGISTER ESP_REG_NUM 98 /* index_base_byte.base for no base register addressing */ 99 #define NO_BASE_REGISTER EBP_REG_NUM 100 #define NO_BASE_REGISTER_16 6 101 102 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ 103 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ 104 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) 105 106 /* Extract fields from the mod/rm byte. */ 107 #define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3) 108 #define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7) 109 #define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7) 110 111 /* Extract fields from the sib byte. */ 112 #define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3) 113 #define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7) 114 #define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7) 115 116 /* x86-64 extension prefix. */ 117 #define REX_OPCODE 0x40 118 119 /* Non-zero if OPCODE is the rex prefix. */ 120 #define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE) 121 122 /* Indicates 64 bit operand size. */ 123 #define REX_W 8 124 /* High extension to reg field of modrm byte. */ 125 #define REX_R 4 126 /* High extension to SIB index field. */ 127 #define REX_X 2 128 /* High extension to base field of modrm or SIB, or reg field of opcode. */ 129 #define REX_B 1 130 131 /* max operands per insn */ 132 #define MAX_OPERANDS 5 133 134 /* max immediates per insn (lcall, ljmp, insertq, extrq) */ 135 #define MAX_IMMEDIATE_OPERANDS 2 136 137 /* max memory refs per insn (string ops) */ 138 #define MAX_MEMORY_OPERANDS 2 139 140 /* max size of insn mnemonics. */ 141 #define MAX_MNEM_SIZE 20 142 143 /* max size of register name in insn mnemonics. */ 144 #define MAX_REG_NAME_SIZE 8 145 146 #endif /* OPCODE_I386_H */ 147
