| /external/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 61 int OpIdx = TII->getOperandIdx(*OldMI, Op);
62 if (OpIdx > -1) {
63 uint64_t Val = OldMI->getOperand(OpIdx).getImm();
|
| AMDGPUISelDAGToDAG.cpp | 188 unsigned OpIdx = Desc.getNumDefs() + OpNo;
189 if (OpIdx >= Desc.getNumOperands())
191 int RegClass = Desc.OpInfo[OpIdx].RegClass;
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeEmitterGen.cpp | 87 unsigned OpIdx;
88 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
90 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
91 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
114 OpIdx = NumberedOp++;
117 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
128 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
134 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
193 unsigned OpIdx;
[all...] |
| CodeGenInstruction.cpp | 137 unsigned OpIdx;
138 if (hasOperandNamed(Name, OpIdx)) return OpIdx;
144 /// given name. If so, return true and set OpIdx to the index of the
146 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const {
150 OpIdx = i;
173 unsigned OpIdx = getOperandNamed(OpName);
177 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp &&
183 return std::make_pair(OpIdx, 0U);
187 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 56 /// For non-data-dependent uses, OpIdx == -1.
59 int OpIdx;
62 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
|
| /external/llvm/lib/CodeGen/ |
| ExecutionDepsFix.cpp | 201 bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
473 bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
475 unsigned reg = MI->getOperand(OpIdx).getReg();
559 unsigned OpIdx = UndefReads.back().second;
566 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg()))
567 TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);
574 OpIdx = UndefReads.back().second;
|
| MachineInstr.cpp | [all...] |
| TargetInstrInfo.cpp | 677 unsigned OpIdx[4][4] = {
693 MachineOperand &OpA = Prev.getOperand(OpIdx[Row][0]);
694 MachineOperand &OpB = Root.getOperand(OpIdx[Row][1]);
695 MachineOperand &OpX = Prev.getOperand(OpIdx[Row][2]);
696 MachineOperand &OpY = Root.getOperand(OpIdx[Row][3]);
[all...] |
| /external/llvm/lib/ExecutionEngine/RuntimeDyld/ |
| RuntimeDyldChecker.cpp | 254 unsigned OpIdx = OpIdxExpr.getValue();
255 if (OpIdx >= Inst.getNumOperands()) {
258 ErrMsgStream << "Invalid operand index '" << format("%i", OpIdx)
267 const MCOperand &Op = Inst.getOperand(OpIdx);
271 ErrMsgStream << "Operand '" << format("%i", OpIdx) << "' of instruction '"
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 388 unsigned OpIdx = 0;
390 bool DstIsDead = MI.getOperand(OpIdx).isDead();
391 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
403 MIB.addOperand(MI.getOperand(OpIdx++));
406 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
410 MIB.addOperand(MI.getOperand(OpIdx++));
417 SrcOpIdx = OpIdx++;
420 MIB.addOperand(MI.getOperand(OpIdx++));
421 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
